Reset - Xilinx DPU IP Product Manual

Chapter 4: Clocking and Resets

Reset

There are three input clocks for the DPU IP, each of which has a corresponding reset. You must
guarantee each pair of clocks and resets is generated in a synchronous clock domain. If the related
clocks and resets are not matched, the DPU might not work properly. A recommended solution is to
instantiate a Processor System Reset IP to generate a matched reset for each clock. The reference
design is shown in Figure 16.
Figure 16: Reference Design for Resets
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PG338 (v1.2) March 26, 2019