Intel - Intel VC820 - Desktop Board Motherboard Design Manual

System Design Considerations
®
6.1.2

Intel

Delivery
Figure 6-1
power delivery architecture supports the "Instantly Available PC Design Guidelines" via the
suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices
include: main memory, the ICH resume well, PCI wake devices (via 3.3V aux) and USB (USB can
only be powered if sufficient standby power is available). To ensure that enough power is available
during STR, a thorough power budget must be completed. The power requirements must include
each device's power requirements, both in suspend and in full-power. The power requirements
must be compared against the power budget supplied by the power supply. Due to the requirements
of main memory and PCI 3.3V aux (and possibly other devices in the system), it is necessary to
create a dual power rail.
®
Figure 6-1. Intel 820 Chipset Power Delivery Example
5VSB
5V Dual
Switch
The examples given in this Design Guide are only examples. There are many power distribution
methods that achieve the similar results. It is critical, when deviating from these examples in any
way, to consider the effect of the change.
6-2
820 Chipset Customer Reference Board Power
shows the power delivery architecture for the Intel
ATX P/S
VRM
with 1A 5VSB
5V 3.3V 12V
VTT Regulator
2.5V
Regulator
CK133-2.5: 2.5V
CK133-3.3: 3.3V
1.8V Regulator
VDDQ
Regulator
3.3VSB
Regulator
USB Cable Power: 5V
1A S0, S1; 1mA S3, S5
AC'97 Modem Codec: 5V
* Vddq also connects to the AGP connector. 2A is the TOTAL VDDQ current requirement.
** Actual MCH and ICH hub interface max. power is 110 mA. However, only one of the devices may be driving the bus at any given time (i.e., only one will
be consuming 110 mA). Therefore, 55 mA has been budgeted to each device. The MCH hub interface I/O power is accounted for in the 2A, 1.8V requirement
Shaded regulators/components are on in S3, S5 (Note RDRAM core and VCC CMOS must be OFF in S5)
LEGEND:
ATX Power Planes
5VSB
5V
3.3V
12V
®
Slot1 Core: VCC_VID
18.6A S0, S1
Slot1 VTT: 1.5V
2.7A S0, S1
Slot1 VCC5: 5V
1A S0, S1
Slot1 VCC3: 3.3V
1.8A S0, S1
MCH Core: 1.8V
MCH Hubinterface I/O: 1.8V
950mA S0, S1
RDRAM VTerm: 1.8V
MCH VDDQ: 1.5V/3.3V*
704mA S0, S1
2A S0, S1
ICH Core: 3.3V
2.5V CPU CMOS
300mA S0, S1 Regulator (STR)
ICH Hubinterface I/O: 1.8V**
55mA S0, S1
ICH 5V Rail: 5V
1.5A S0, S1; 435ma S3, S5
ICH Resume: 3.3V
10mA S0, S1; 300uA S3, S5
LPC Super I/O: 3.3V
ICH RTC: Vbat
5uA S0, S1, S3, S5
FWH Flash BIOS
Core: 3.3V
67mA S0, S1
Intel ® 820 Chipset Power Planes
5V Dual 1.8V
VCCVID VDDQ
VTT 3.3VSB
2.5V
2.5VSBY
820 Chipset Reference Board. This
DRCG: 3.3V
100mA S0, S1
RDRAM Core: 2.5V
4.5A S0, S1; 32ma S3
VCC CMOS: 1.8V
3mA S0, S1, S3
Processor |
CMOS P/Us: 2.5V
PCI 3.3Vaux: 3.3V
®
Intel 820 Chipset Design Guide
2.5V
1.8V