Agp 2.0 - Intel VC820 - Desktop Board Motherboard Design Manual

2.7

AGP 2.0

For detailed AGP Interface functionality (protocols, rules and signaling mechanisms, etc.) refer to
the latest AGP Interface Specification revision 2.0, which can be obtained from
www.agpforum.org. This document focuses only on specific Intel
recommendations.
The AGP Interface Specification revision 2.0 enhances the functionality of the original AGP
Interface Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and
1.5 volt operation. In addition to these major enhancements, additional performance enhancement
and clarifications, such as fast write capability, are included in the AGP Interface Specification,
Revision 2.0. The Intel
AGP 2.0.
The 4X operation of the AGP interface provides for "quad-pumping" of the AGP AD (Address/
Data) and SBA (Side-band Addressing) buses. That is, data is sampled four times during each
66 MHz AGP clock. This means that each data cycle is ¼ of a 15 ns (66 MHz) clock or 3.75 ns. It
is important to realize that 3.75 ns is the data cycle time, not the clock cycle time. During 2X
operation, data is sampled twice during a 66 MHz clock cycle; therefore, the data cycle time is
7.5 ns.
To allow for these high speed data transfers, the 2X mode of AGP operation uses source
synchronous data strobing (refer to
During 4X operation, the AGP interface uses differential source synchronous strobing.
With data cycle times as small as 3.75 ns, and setup/hold times of 1 ns, propagation delay
mismatch is critical. In addition to reducing propagation delay mismatch, it is important to
minimize noise. Noise on the data lines will cause the settling time to be large. If the mismatch
between a data line and the associated strobe is too great, or there is noise on the interface,
incorrect data will be sampled.
The low-voltage operation on AGP (1.5V) requires even more noise immunity. For example,
during 1.5V operation, V
integrity issues.
®
Intel 820 Chipset Design Guide
®
820 chipset is the first Intel chipset that supports the enhanced features of
Section 2.5, "Source Synchronous Strobing" on page
is 570 mv. Without proper isolation, crosstalk could create signal
ilmax
Layout/Routing Guidelines
http://
®
820 chipset platform
2-5).
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