Intel VC820 - Desktop Board Motherboard Design Manual page 207

8 7
Processor Connector 0
D ITP
VCC3_3 VCC2_5 VTT1_5
ITP_PU_R
J26
R95
4,6,8 CPURST# CPURST#_R 1
240
DBRESET# 3
C
33
5
7
9
11
XREF=6
TMS_R TCK_R 13
15
6
17
19
21
23
25
27
ITPCLK 29
7
B
R7 and R11 should be placed within 1" of ITP connector.
VCC12
CPU TACH0
C36
VCC2_5
JP31
1
2
3
A
1
4,6 TDO_0
3
6 TDO_1
8 7
6
VCC2_5 VTT1_5
2
4
6
8 TDI
10 TDO
12 TRST# 6
14
16 ITPREQ#
4
18 ITPRDY#_R
20 ITPREQ1# 6
22 ITPRDY1#_R
24
26
28
30
ITPPRDY# 4 33
6
ITPRDY1#
TCK 6
TMS
VCC2_5
ITP Config JP33 JP34
Single CPU0 1-2 1-2
Dual CPU 2-3 1-2
Single CPU1 2-3 2-3
JP33 JP34
1
2 TDO 4 4 TDI 2
3
6
5 4
VTT1_5 VCCVID
J15
A25 DEP#0
A27 DEP#1
B26 DEP#2
A28 DEP#3
B27 DEP#4
VCC3_3
A29 DEP#5
A31 DEP#6
B28 DEP#7
4
4 R376 B19 BP2#
A21 BP3#
A23 BPM0#
8.2K
B24 BPM1#
BINIT# A24 BINIT#
6
PICD0 A19 PICD0
6,10,34
PICD1 B22 PICD1
6,10,34
PICCLK B18 PICCLK
7
SLOTOCC0# B101 SLOTOCC#
4 TDI_0 A9 TDI
4,6 TDO_0 A11 TDO
B11 TRST#
B7 TCK
B10 TMS
EMI1 B61 EMI_1
EMI2 B100 EMI_2
EMI3 B81 EMI_3
EMI4 B1 EMI_4
EMI5 B41 EMI_5
CPUHCLK A75 BCLK
6,7
PWRGOOD A12 PWRGOOD
6,33
CPURST# B74 RESET#
4,6,8
TDI_0 4
5 4
3 2
VCC5 VCC3_3
AP0# A117
AP1# B116
BNR# A101
BPRI# A103
TRDY# A104
DEFER# A105
LOCK# B106
DRDY# B107
HITM# A109
HIT# B110
DBSY# A111
HADS# A115
SC242
PREQ# A20
PRDY# B23
BREQ0# A76
BREQ1# B75
RES4 B76
TESTHI A13 TESTHI
BSEL0 B21
BSEL1 A14 SEL133/100#
FLUSH# B2
THMTRP# A15
A20M# A5
STPCLK# B6
SLP# B8
SMI# B3
LINT0 A17
LINT1 B16
INIT# B4
FERR# A7
IGNNE# A8
IERR# A4
BERR# A77
AERR# B118
RES0 A16
RES1 B20
RES2 B112
RES3 A113
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
PROCESSOR CONNECTOR
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630
3 2
1
D
BNR#
6,8
BPRI#
6,8
HTRDY#
6,8
DEFER#
6,8
HLOCK#
6,8
DRDY#
6,8
HITM#
C
6,8
HIT#
6,8
DBSY#
6,8 VCC3_3
HADS#
6,8
ITPREQ#
4
ITPPRDY#
4
R375
BREQ#0
6
BREQ#1
6
220
34
6,7,9
FLUSH#
6,34
A20M#
6,10,34
B
STPCLK#
6,10,34
SLP#
6,10,34
SMI#
6,10,34
LINT0
6,10,34
LINT1
6,10,34
HINIT#
6,10,12,34
FERR#
6,10,34
IGNNE#
6,10,34
A
REV:
3.03
DRAWN BY: PROJECT:
LAST REVISED: SHEET:
11-29-1999_14:45 4 OF 38
1