64/72Mbit Rdram Excessive Power Consumption - Intel VC820 - Desktop Board Motherboard Design Manual

System designers need to be aware of this requirement while designing the voltage regulators and
selecting the power supply. For further details on the voltage sequencing requirements, refer to the
latest Intel
3.3VSB
The 3.3VSB plane powers the suspend well of the ICH and the PCI 3.3Vaux suspend power pins.
The 3.3Vaux requirement state that during suspend, the system must deliver 375mA to each wake-
enabled card and 20 mA to each non wake-enabled card. During full-power operation, the system
must be able to supply 375 mA to EACH card. Therefore, the total current requirement is:
•
Full-power Operation:
•
Suspend Operation:
In addition to the PCI 3.3V aux, the ICH suspend well power requirements must be considered as
shown in
Note: This regulator is required in ALL designs.
2.5V
The 2.5V plane powers the CPU CMOS pull-up resistors. These pull-up resistors must not be
powered when the system is in S3 (because the ICH core is powered down). Therefore, this power
plane must be separate from the 2.5VSBY regulator. The total current requirement is
approximately 180 mA. This power plane could also be implemented using a FET switch from
2.5VSBY (and controlled by SLP_S3#). If using a FET switch, the resistive drop across the FET
switch should be considered.
Note: This regulator is not required in a Intel
to-RAM (STR).
6.1.3

64/72Mbit RDRAM Excessive Power Consumption

Some 64/72Mbit RDRAM devices interpret non-broadcast, device-directed commands as
broadcast commands. These commands are the SET_FAST_CLOCK, SET_RESET, and
CLEAR_RESET commands. RDRAM devices consume more current during these initialization
steps than during normal operation. As a result of these devices accepting device directed
commands as broadcast commands, the device can not be reset/initialized serially. All devices must
be reset/initialize simultaneously. This will result in excessive current draw during the initialization
of memory. The amount of excessive current will depend on the number of devices and frequency
used. The worst case current draw is 7.5A, in a system with 32 devices and a frequency of
400 MHz. There are two potential solutions:
1. Reduce the clock frequency during initialization
Frequency During Initialization" on page
2. Increase the current capability of the 2.5V voltage regulator
Increase the Current Capability of the 2.5V Voltage Regulator" on page
®
Intel 820 Chipset Design Guide
®
820 Chipset: 82820 Memory Controller Hub (MCH) datasheet.
375 mA * number of PCI slots
375+20 * (number of PCI slots – 1)
Figure 6-1.
®
820 chipset based system that does not support Suspend-
(Section 6.1.3.1, "Option 1: Reduce the Clock
6-6);
System Design Considerations
(Section 6.1.3.2, "Option 2:
6-6).
6-5