Component Placement And Interconnection Layout Requirements; 14.318 Mhz Crystal To Ck133; Ck133 To Drcg; Ck133 To Drcg Routing Diagram - Intel VC820 - Desktop Board Motherboard Design Manual

Clocking
4.2 Component Placement and Interconnection Layout
Requirements
Detailed explanation of layout requirements for each interconnections are provided in the
following sections:
•
Crystal to CK133
•

CK133 to DRCG

•
MCH to DRCG
•
DRCG to RDRAM channel
4.2.1

14.318 MHz Crystal to CK133

The distance between the crystal and the CK133 should be minimized. The maximum trace length
is 500 mils.
4.2.2 CK133 to DRCG
•
CPU_div2
•
VDDIR – Used as a reference for 2.5V signaling
Figure 4-3. CK133 to DRCG Routing Diagram
6 mils
Ground
4.5 mils
VddIR and CPU_div2 must be routed as shown in
connected directly to 2.5V near the DRCG if the 2.5V plane extends near the DRCG. However, if a
2.5V trace must be used, it should originate at the CK133 and be routed as shown.
4-6
6 mils
VddiR
6 mils 6 mils
Ground/Power Plane
6 mils 6 mils
CPU_div2
Ground
6 mils
Figure 4-3. Note that the VddiR pin can be
Intel
6 mils
Ground 1.4 mils
6 mils
1.4 mils
®
820 Chipset Design Guide