Intel VC820 - Desktop Board Motherboard Design Manual page 214

8 7
VCC3_3SBY
ICH
A
+
-
C
R245
D
1K
VBAT_CR JP20
1
RTC_RST_JP
3
R241
RTC_CLR
C
-
8.2K
+
A
R250
VBAT_RC
1K
C249
VBAT_RTC
C
R247
BAT1
10M
R249
Use CR2032 battery. 10M
Y4
XTAL
2
32.768KHZ
C250
S tra p JP 26
No W D Reboot IN
B
23 PCI_TEST
Reboot on W D* O UT
7 DRCG_CTRL
S tra p JP 5
S afe M ode IN
ICH s trap* O UT
CM O S JP 20
Norm al* 1-2
11,20
Clear 2-3
A
SPKR_STRAP
8 7
6
VCC_RTC_JP
VCC3_3
R231
THRM# 3,5
8.2K SLP_S3#
31,33
SLP_S5#
32
VCC3_3 PWROK
9,18,31,33
PWRBTN#
20
ICH_RI#
27
2 RSMRST#
19,33
MULT1_GPIO
7,14
GPIO26_FPLED
20
SMBDATA_CORE
3,5,13,34
SMBCLK_CORE
3,5,13,34
SMB_ALERT
34
LPC_SMI#
14
LPC_PME#
14
R232
INTRUDER#
8.2K
RTCRST#
VBIAS
RTCX1
RTCX2
ICH_CLK66
7
ICH_14MHZ
7
ICH_48MHZ
7
AC_RST#
17
AC_SYNC
15,17
AC_BITCLK
1
15,17
AC_SDATAOUT
11,15,17
C251
AC_SDATAIN0
15,17
AC_SDATAIN1
17
SPKR
11,20
R212
GPIO12
R215
8.2K GPIO13
8.2K GPIO21
MULT0_GPIO
7
GPIO23_FPLED
R98
20
ALERTCLK_SBY
0K 18,34
ALERTDATA_SBY
18,34
R162
LAD0/FWH0
0K 12,14
LAD1/FWH1
12,14
VCC3_3SBY LAD2/FWH2
12,14
LAD3/FWH3
12,14
LDRQ#0
14
R238
GPIO8
8.2K LFRAME#/FWH4
12,14
SPKR
VCC3_3
USBP1P
25
USBP1N
25
JP26
USBP0P
25
USBP0N
25
OC#1
25
2.7K
OC#0
25
AC_SDOUT_STRAP
2.7K
JP5
AC_SDATAOUT
11,15,17
6
5 4
VCC3_3SBY
U13
ICH_096
D14
THRM#
K3
GPIO24/SLP_S3#
K2
SLP_S5#
J3
PWROK
M2
PWRBTN#
L3
RI#
F1
RSMRESET#
L4
GPIO25/SUSSTAT#
K4
SUSCLK/GPIO26
J1
SMBDATA
J2
SMBCLK
M1
GPIO11/SMBALERT#
SYSTEM
E11
GPIO6
D11
GPIO5
J4
GPIO10/INTRUDER#
H1
RTCRST#
ICH_B
H2
VBIAS
H3
RTCX1
H4
RTCX2
A16
CLK66
U6
CLK14
U2
CLK48
T1
AC_RST#
T3
AC_SYNC
R3
AC_BIT_CLK
AC97
T2
AC_SDOUT
U1
ACSDIN0
P3
GPIO9/AC_SDIN1
U3
SPKR
N4
GPIO12
L2
GPIO13
GPIO
B14
GPIO21
D13
GPIO22
D15
GPIO23
M5
GPIO27/ALERT_CLK
L5
GPIO28/ALERT_DATA
R6
LAD0/FWH0
U5
LAD1/FWH1
T5
LAD2/FWH2
LPC
T4
LAD3/FWH3
T6
LDRQ0#
N3
GPIO8/LDRQ1#
U4
LFRAME#/FWH4
R1
USBP1+
P2
USBP1-
P1
USBP0+
USB
N2
USBP0-
M4
OC1#
M3
OC0#
5 4
3 2
VCC5_REF
C233
PDCS#1
N12
PDCS1#
24
SDCS#1
L14
SDCS1#
24
PDCS#3
U13
PDCS3#
24
SDCS#3
L16
SDCS3#
24
PDA0
R12
PDA0
T12 PDA1
PDA1 PDA[2:0]
PDA2
P12
PDA2
SDA0
M16
SDA0
SDA1
M15
SDA1
SDA[2:0]
SDA2
L13
SDA2
PDREQ
U11
PDDREQ
24
SDREQ
P17
SDDREQ
24
U12 PDDACK#
PDDACK#
24
SDDACK#
M13
SDDACK#
24
R11 PDIOR#
PDIOR#
24
N16 SDIOR#
SDIOR#
24
T11 PDIOW#
PDIOW#
24
N15 SDIOW#
SDIOW#
24
N11 PIORDY
PIORDY
24
N17 SIORDY
SIORDY
24
PDD[15:0]
R10 PDD0
PDD0
PDD1
N9
PDD1
PDD2
R9
PDD2
PDD3
U9
PDD3
PDD4
R8
PDD4
PDD5
U8
PDD5
PDD6
R7
PDD6
U7 PDD7
PDD7
PDD8
P7
PDD8
PDD9
N7
PDD9
IDE
PDD10
T8
PDD10
PDD11
P8
PDD11
T9 PDD12
PDD12
PDD13
P9
PDD13
PDD14
T10
PDD14
PDD15
P10
PDD15
SDD[15:0]
SDD0
P15
SDD0
SDD1
R16
SDD1
SDD2
T17
SDD2
SDD3
U16
SDD3
SDD4
U15
SDD4
SDD5
R14
SDD5
SDD6
P13
SDD6
SDD7
T13
SDD7
SDD8
U14
SDD8
SDD9
T14
SDD9
SDD10
P14
SDD10
SDD11
T15
SDD11
SDD12
U17
SDD12
SDD13
R15
SDD13
SDD14
R17
SDD14
SDD15
P16
SDD15
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
ICH
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630
3 2
1
VCC3_3 VCC5
A
+
-
C
D
24
24
C
24
B
24
A
REV:
3.03
DRAWN BY: PROJECT:
LAST REVISED: SHEET:
11-29-1999_14:46 11 OF 38
1