Intel VC820 - Desktop Board Motherboard Design Manual page 76

Layout/Routing Guidelines
Table 2-13. Processor and 82820 MCH Connection Checklist
CPU Pin
CMOS Signals
A20M#
FERR#
FLUSH#
IERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI
PICD[1:0]
PREQ#
PWRGOOD
SLP#
SMI#
STPCLK#
THERMTRIP#
TAP Signals
PRDY#
TCK
TDO
TDI
TMS
TRST#
2-50
UP Pin Connection (CPU0)
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5 (not used by chipset). Connect to 2
150 Ω pull up to Vcc2.5 if tied to custom logic
or leave as N/C (not used by chipset).
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH and
FWH Flash BIOS
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH
~200–330 Ω pull up to Vcc2.5, connect to ITP
pin 16
150–330 Ω pull up to 2.5V, output from the
PWRGOOD logic
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5, connect to ICH
150 Ω pull up to Vcc2.5 and connect to power
off logic or ASIC, or leave as N/C
150 Ω pull up to V , 240 Ω series resistor to
TT
ITP pin 18
1k Ω pull up to Vcc2.5, 47 Ω series resistor to
ITP pin 5
150 Ω pull up to Vcc2.5 and connect to ITP
10
~150–330 Ω pull up to Vcc2.5 and connect to
ITP pin 8
1 KΩ pull up to Vcc2.5, 47 Ω series resistor
to ITP pin 7
~680 Ω pull down, connect to ITP pin 12
1,2
(Continued)
DP Pin Connection (CPU1)
nd
Connect to 2 processor
nd
Connect to 2 processor
nd
processor
nd
Connect to 2 processor
nd
Connect to 2 processor
nd
Connect to 2 processor
nd
Connect to 2 processor
nd
Connect to 2 processor
Two 300–330 Ω pull ups to Vcc2.5 located
at each end of trace. Connect to 2
processor
~200–330 Ω pull up to Vcc2.5, connect to
ITP pin 20
nd
Connect to 2 processor
nd
Connect to 2 processor. Could tie
separately to a monitoring ASIC.
150 Ω pull up to V , 240 Ω series resistor
TT
to ITP pin 22
Each processor should receive a
separately buffered copy of TCK from the
ITP. Tank circuit is optional for signal
integrity. See
TDO of CPU1 is connected to the ITP TDO
pin 10. Pull up both sets of TDI/TDO nets
as described.
TDI of CPU0 is connected to the ITP pin 8,
TDI of CPU1 is connected to TDO of
CPU0. Pull up both sets of TDI/TDO nets
as described.
Each processor should receive a
separately buffered copy of TMS from the
ITP.
Tank circuit is optional for signal integrity.
See
nd
Connect to 2 processor
®
Intel 820 Chipset Design Guide
nd