One Signal Layer And One Reference Plane; Layer Switch With One Reference Plane; Layer Switch With Multiple Reference Planes (Same Type) - Intel VC820 - Desktop Board Motherboard Design Manual

change the impedance of adjacent trace layers. (For instance, the impedance calculations may have
been done for microstrip geometry, and adding a partial plane on the other side of the trace layer
may turn the microstrip into a stripline.)
3.4.3.2 Reference Planes and PCB Stackup
It is strongly recommended that baseboard stackup be arranged such that AGTL+ signals are
referenced to a ground (VSS) plane, and that the AGTL+ signals do not traverse multiple signal
layers. Deviating from either guideline can create discontinuities in the signal's return path that can
lead to large SSO effects that degrade timing and noise margin. Designing an AGTL+ platform
incorporating discontinuities will expose the platform to a risk that is very hard to predict in pre-
layout simulation.
within the same signal layer, with a ground layer as the single reference plane.
Figure 3-6. One Signal Layer and One Reference Plane
When it is not possible to route the entire AGTL+ signal on a single VSS referenced layer, there
are methods to reduce the effects of layer switches. The best alternative is to allow the signals to
change layers while staying referenced to the same plane (see
another method of minimizing layer switch discontinuities, but may be less effective than
Figure 3-7. In this case, the signal still references the same type of reference plane (ground). In
such a case, it is important to stitch (i.e., connect) the two ground planes together with vias in the
vicinity of the signal transition via.
Figure 3-7. Layer Switch with One Reference Plane
Figure 3-8. Layer Switch with Multiple Reference Planes (same type)
®
Intel 820 Chipset Design Guide
Figure 3-6 shows the ideal case where a particular signal is routed entirely
Signal Layer A
Ground Plane
Signal Layer A
Ground Plane
Signal Layer B
Signal Layer A
Ground Plane
Layer
Layer
Ground Plane
Signal Layer B
Advanced System Bus Design
1lay 1ref plane vsd
Figure 3-7).
l 1 f l d
l M lt f l d
Figure 3-8 shows
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