Initial Timing Analysis - Intel VC820 - Desktop Board Motherboard Design Manual

Chipset
Table of Contents

Advertisement

3.2.1

Initial Timing Analysis

Perform an initial timing analysis of the system using
These equations are the basis for timing analysis. To complete the initial timing analysis, values for
clock skew and clock jitter are needed, along with the component specifications. These equations
contain a multi-bit adjustment factor, M
pushout or pull-in that are often hard to simulate. These equations do not take into consideration all
signal integrity factors that affect timing. Additional timing margin should be budgeted to allow for
these sources of noise.
Equation 3-1. Setup Time
Equation 3-2. Hold Time
Symbols used in
— T
— T
— CLK
— CLK
— T
Definitions" on page
— T
Definitions" on page
— M
— T
— T
Note: The Clock to Output (T
last crossing of V
rate limits. See the respective Processor's datasheet and thePentium® III Processor Developer's
Manual for more details.
Solving these equations for T
Equation 3-3. Maximum Flight Time
Equation 3-4. Minimum Flight Time
®
Intel
820 Chipset Design Guide
T
+ T
CO_MAX
SU_MIN
T
+ T
FLT_MIN -
CO_MIN
Equation 3-1
and
Equation
is the maximum clock to output specification
CO_MAX
is the minimum required time specified to setup before the clock
SU_MIN
is the maximum clock edge-to-edge variation.
JITTER
is the maximum variation between components receiving the same clock edge.
SKEW
is the maximum flight time as defined in
FLT_MAX
3-1.
is the minimum flight time as defined in
FLT_MIN
3-1.
is the multi-bit adjustment factor to account for SSO pushout or pull-in.
ADJ
is the minimum clock to output specification
CO_MIN
is the minimum specified input hold time.
HOLD
) and Setup to Clock (T
CO
, with the requirement that the signal does not violate the ringback or edge
REF
results in the following equations:
FLT
≤ Clock Period - T
T
FLT_MAX
≥ T
T
FLT_MIN
HOLD
Equation 3-1
, to account for multi-bit switching effects such as SSO
ADJ
+ CLK
+ CLK
SKEW
JITTER
≥ T
M
+ CLK
ADJ
HOLD
SKEW
3-2:
Section 3.1, "Terminology and
Section 3.1, "Terminology and
) timings are both measured from the signals
SU
- T
CO_MAX
SU_MIN
+ CLK
- T
+ M
SKEW
CO_MIN
Advanced System Bus Design
and
Equation 3-2
shown below.
≤ Clock Period
+ T
+ M
FLT_MAX
ADJ
.
1
.
1
.
1
- CLK
- CLK
SKEW
JITTER
ADJ
- M
ADJ
3-5

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

820

Table of Contents