High-Speed Cmos Termination; Sio Routing Example - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
Figure 2-26. High-Speed CMOS Termination
2.6.4.1 SIO Routing
The SIO signal must be routed from RIMM to RIMM as shown in
requires a 2.2 KΩ – 10 KΩ terminating resistor on the SOUT pin of the last RIMM. SIO is routed
with a standard 5 mil wide 60 Ω trace. The motherboard routing lengths for the SIO signal are the
same as RSL signals (see
Figure 2-27. SIO Routing Example
2.6.4.2 Suspend-to-RAM Shunt Transistor
When an Intel
MCH (i.e., it will be powering-up or powering-down). When power is ramping, the state of the
MCH outputs is not guaranteed. Therefore, the MCH could drive the CMOS signals and issue
CMOS commands. One of the commands (the only one the RDRAMs would respond to) is the
powerdown exit command. To avoid the MCH inadvertently taking the RDRAMs out of power-
down due to the CMOS interface being driven during power ramp, the SCK (CMOS clock) signal
must be shunted to ground when the MCH is entering and exiting Suspend-to-RAM. This shunting
can be accomplished using the NPN transistor shown in circuit shown in
transistor should have a Cobo of 4 pf or less (i.e., MMBT3904LT1).
In addition, to match the electrical characteristics on the SCK signal, the CMD signal needs a
dummy transistor. This transistor's base should be tied to ground (i.e., always turned off).
2-26
MCH
Figure 2-17).
SIN B36
82820
MCH
A
0" - 3.50"
®
820 chipset system enters or exits Suspend-to-RAM, power will be ramping to the
RIMM_0 RIMM_1
N N
3 3
2 2
A36 SOUT
1 1
SIN B36
B
0.4" - 0.45"
Vterm
91 Ω
R1
39 Ω
R2
Figure 2-17. The SIO signal
A36 SOUT
2.2KΩ -
10KΩ
Figure 2-28. The
®
Intel 820 Chipset Design Guide