Clocking
4.3
DRCG Impedance Matching Circuit
The external DRCG impedance matching circuit is shown in
elements are listed in
Figure 4-9. DRCG Impedance Matching Network
C
D
C
D
C
D
C
D
Table 4-5. External DRCG Component Values
Component
C
MID
FBead
CD2
CBulk
NOTES:
1. The ferrite bead and 10 uF bulk cap combination improves jitter and helps to keep the clock noise away from
the rest of the system.
2. 0.1 uF capacitors are better than 0.01 uF or 0.001 uF caps for DRCG decoupling.
The circuit shown in
channel impedance. More detailed information can be found in the Direct Rambus Clock Generator
Specification.
4-10
Table
4-5.
V
V
O
IR
DD
DD
V
DD P
DRCG
V
C
DD
V
IPD
DD
V
O
DD
Nominal Value
C
0.1 uF
D
R
39 Ohms
S
R
51 Ohms
P
, C
0.1 uF
MID2
R
27 Ohms
T
C
4 pF
F
50 Ohms at 100 MHz
0.1 uF
10 uF
is required to match the impedance of the DRCG to the 28 Ω
Figure 4-9
To 3.3V DRCG
Supply Connection
CD2
C
D
R
R
S
P
C
MID
C
F
R
R
P
S
C D
1,2
Decoupling caps to ground
Series termination resistor
Parallel termination resistor
Virtual ground caps
End of channel termination
Do not stuff
Ferrite bead
Additional 3.3V decoupling caps
Bulk cap on device side of ferrite bead
Figure
4-9. The values for the
FBead
CD2
CBulk
Z
R
CH
T
Z
R
CH
T
Notes
®
Intel
820 Chipset Design Guide
3.3v
C
MID2