Intel VC820 - Desktop Board Motherboard Design Manual page 210

8 7
Clock Synthesizer
VCC3_3
L20
1 2
FBHS01L
VCC_3_3_CK133_FB
C207 C215 C223 C186 C198 C206 C214 C170
D
VCC3_3
VCC3_3
C185
10PF
220
4,6,9 SEL133/100#
PCISTOP#
CPUSTOP#
CK133_PWRDWN#
SPREAD#
C
SEL1
SEL0
JP17 JP15 JP14
H O S T
B
B U S / R A M B U S J P 1 3 J P 1 8
1 0 0 / 3 0 0 2 -3 O U T
1 0 0 / 4 0 0 O U T O U T
1 3 3 / 4 0 0 2 -3 O U T
G P O C N T R L * 1 -2 O U T
S p r d S p e c t J P 1 4
E n a b le d * IN
D is a b le d O U T
SEL133/100# JP15 JP17
0 IN IN All outputs Tri-State
0 IN OUT Reserved
0 OUT IN Active 100MHz, 48MHz PLL inactive
A
0 OUT OUT Active 100MHz, 48MHz PLL active
1 IN IN Test Mode
1 IN OUT Reserved
1 OUT IN Active 133MHz,48MHz PLL inactive
1 OUT OUT Active 133MHz,48MHz PLL active*
All jumpers may not be required, but are included for test purposes.
8 7
6
Provide at least one 0.1uF decoupling cap per power pin.
U11
CK133
CK133_XIN
Y3
XTAL
CK133_XOUT
1 2
14.318MHZ
C189
10PF
CPU_DIV2_1
5
XTAL_IN
CPU_DIV2_2
6
XTAL_OUT
28
SEL133/100#
37
PCISTOP#
36
CPUSTOP#
35
PWRDWN#
34
SPREAD#
33
SEL1
32
SEL0
VCC3_3
Function 11 DRCG_CTRL
JP11
No stuff R161, JP11.
6
5 4
VCC2_5_CK133_FB
C180
R155
PICCLK_R 22 PICCLK
53
APIC0
R156
APICCLK_R 22 APICCLK
54
APIC1
PICCLK1_R 22 PICCLK1
55
APIC2
R148
CPU_DIV2_1_R 22 CPU_DIV2
50 R151
CPU_DIV2_2_R
49
R188
ITPCLK_R 22 ITPCLK
41
CPUCLK0
R189
CPUHCLK_R 22 MCHCLK
42
CPUCLK1
R184
22 CPUHCLK
45
CPUCLK2
CPUHCLK1_R 22 CPUHCLK1
46 R170
CPUCLK3
R165
ICHPCLK_R 33 ICHPCLK
8
PCICLK_F
R164
9 PCLK1_R 33 PCLK1
PCICLK1
R169
PCLK2_R 33 PCLK2
11
PCICLK2
R183
12 PCLK3_R 33 PCLK3
PCICLK3
R186
14 PCLK4_R 33 PCLK4
PCICLK4
R187
15 PCLK5_R 33 PCLK5
PCICLK5
R191
17 FWHPCLK_R 33 FWHPCLK
PCICLK6
R194
18 SIO_PCLK7_R 33 SIO_PCLK7
PCICLK7
R201
MCH_CLK66_R 33 AGPCLK_CONN
21
3V66_0
R195
22 33 MCH_CLK66
3V66_1
R210
ICH_CLK66_R 33 ICH_CLK66
25
3V66_2
R211
TEST_CLK66_R 33 TEST_CLK66
26
3V66_3
R221
IHC_48MHZ_R 22 ICH_48MHZ
30
48MHZ
R147
IHC_14MHZ_R 22 ICH_14MHZ
2
REF0
R150
SIO_14MHZ_R SIO_14MHZ
3
REF1
22
No stuff R106
VCC3_3
for debug.
VCC1_8
MULT0_GPIO
11
JP13 is for debug only. JP13
1
2
3
JP18
1
11,14 MULT1_GPIO 2
3
5 4
3 2
VCC2_5
L21
1 2
FBHS01L
C190 C192 C199 C171
4
10
6 Keep stubs on unused outputs as short as possible.
Tie CPUCLK and MCHCLK outputs together.
4
8
4,6
6
10
22
22
23
23
18
12
14
21
9 VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
11 CLKTM and CLKTM# RC network must use 5% or better tolerance components.
11
11 VCC2_5
14
VCC1_8
VCC3_3_DRCG_FB
U12
DRCG
2
REFCLK
DRCG_PWRDWN#
12
PWRDN#
STOPB# DRCG_CLK
11
STOPB#
MULT0
15
MULT0
20
CLK
MULT1
14
MULT1
18
CLKB#
24
S0
23
S1
13
GND
HCLKOUT
6
PCLKM
9
RCLKOUT
7
SYNCLKN
9
19
NC
DRCG_CLKB#
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
CLOCK SYNTHESIZER
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630
3 2
1
D
C
VCC3_3
L22
1 2
FBHS01L
C208 C196 C204 C220 C209
B
39-1%
CLKTM
13
R182
51-1% 51-1%
C80
R185 R200
39-1%
CLKTM#
13
R205
No stuff C80
C205
A
REV:
3.03
DRAWN BY: PROJECT:
LAST REVISED: SHEET:
11-29-1999_14:46 7 OF 38
1