Intel VC820 - Desktop Board Motherboard Design Manual page 56

Layout/Routing Guidelines
— ALL RSL, CMD/SCK and CTM/CTM#/CFM/CFM# signals have CTABs on each RIMM
connector pin
— All RSL signals are routed adjacent to a ground reference plane. This includes all signals
from the last RIMM to the termination. If signals are routed on the bottom from the last
RIMM to the termination, the ground reference plane on the 3
these signals AND include the ground side of the Vterm decoupling capacitors.
— CTABs must not cross (or be on top of) power plane splits. They must be ENTIRELY
referenced to ground.
— At least 10 mils ground flood isolation required around ALL RSL signals (ground
isolation must be exactly 6 mils from RSL signals). Ground flood recommended for
isolation. This ground flood should be as close to the MCH (and the 1st RIMM) as
possible. If possible connect the flood to the ground balls/pins on the MCH/connector.
•
Clean V
— Ensure 1 x 0.1 uF capacitor on V
— Use 10 mil wide trace (6 mils minimum)
— Do not route V
•
RSL Routing
— All signals must be length matched within ±10 mils of the Nominal RSL Length (note:
use the table in the Intel
to verify trace lengths). Ensure that signals with a dummy via are compensated correctly.
— ALL RSL signals must have 1 via near the MCH BGA pad. Signals routed on the
secondary side of the MB will have a "real via" while signals routed on the primary side
will have a "dummy via". Additionally, all signals with a dummy via must have an
additional trace length of 25 mils.
— "B" side RIMM connector signals are routed on the secondary side of the motherboard.
"A" side RIMM connector signals are routed on the primary side of the motherboard.
— Signals must "alternate" layers as shown in the following table.
•
Clock Routing
— Clock signals must be routed as a differential pair. The traces must be 14 mils wide and 6
mils apart (with no ground isolation) when they are routed as a differential pair. For very
short sections under the MCH and under the 1st RIMM, it will not be possible to route as
a differential pair. In these sections, the clocks signals MUST neck up to 18 mils and be
ground isolated with at least 10 mils ground isolation.
— Clock signals must be length compensated (using the 1.021 length factor described in
Section 2.7.3, "2X/4X Timing Domain Routing Guidelines" on page
each clock pair is length matched within ±2 mils.
— When clock signals serpentine, they must serpentine together (to maintain differential
14:6 routing).
— 22 mils ground isolation required on each side of the differential pair.
2-30
Routing
REF
near high-speed signals
REF
®
820 chipset: 82820 Memory Controller Hub (MCH) Datasheet
If Signal Routed from MCH to the 1
Primary Side
Secondary Side
at each connector
REF
Then Route Signal from 1
st
RIMM on:
Secondary Side
Primary Side
Intel
rd
layer MUST extend under
st
RIMM to Next
RIMM on:
2-33). Ensure that
®
820 Chipset Design Guide