Dual-Processor Breq Strapping Requirements; Breq0# Circuitry For Dp Systems - Intel VC820 - Desktop Board Motherboard Design Manual

DP Systems: For dual processor systems, BREQ0# (to one of the processors) needs to be driven
for arbitration ID strapping. Refer to
system. It is a requirement that the on-board logic tri-state BREQ0# after the arbitration ID
strapping is complete. Additionally, BREQ0# and BREQ1# are high-speed AGTL+ signals and the
loading characteristics of the on-board logic must be considered even when the logic is tri-stated.
Figure 2-43. Dual-Processor BREQ Strapping Requirements
Figure 2-44. BREQ0# Circuitry for DP Systems
CPURST#
This circuit holds BREQ0 low for two clocks after the deassertion of reset. The 2N3904 connected
to BREQ0 should be connected to the BREQ0 AGTL trace with a very short stub. Additionally, the
series current limiting resistor on CPURESET should be attached to the CPURESET trace with a
very short stub.
External Circuit Recommendation for HA7 Strapping for IOQ Depth of 1
For debug purpose, the external logic to set the IOQ depth of 1 on the front side bus may be
needed. Do not add this circuit for production since overall system performance will be degraded.
The external logic for HA7# strapping is very similar to the BREQ0 strapping that is described in
the previous section.
The timing requirement of HA7# strapping is also similar to BREQ0 strapping for the hold time
after the deassertion of RESET# (RSTIN# signal from MCH). The value of the strapping needs to
be held for a minimum of 2 host clocks after the deassertion of RSTIN#. Refer to the latest version
of the processor datasheets for complete description on the timing requirement.
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Intel 820 Chipset Design Guide
Figure 2-43
CPU #1
BREQ0#
5V
R2
2.7 KΩ Ω Ω Ω
R2
2
4.7 KΩ Ω Ω Ω
2N3904
3
CPUCLK
for an example of the BREQ connections in a DP
CPU #2
BREQ1# BREQ0# BREQ1#
on-board logic
5V 5V
4
4
2
5
D /PRE /PRE
Q D
3
CLK 6 CLK
/Q
/CLR /CLR
1 74F74 1
Layout/Routing Guidelines
4.7 KΩ Ω Ω Ω
5
Q 2N3904
6
/Q
74F74
BREQ0#
2-53