Intel VC820 - Desktop Board Motherboard Design Manual page 7

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Intel 820 Chipset Design Guide
BREQ0# Circuitry for DP Systems..............................................................2-53
HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54
Host-Side IDE Cable Detection...................................................................2-57
Drive-Side IDE Cable Detection..................................................................2-58
Layout for Host- or Drive-Side IDE Cable Detection...................................2-59
Ultra ATA/66 Cable .....................................................................................2-59
Resistor Requirements for Primary IDE Connector ....................................2-60
Resistor Requirements for Secondary IDE Connector ...............................2-61
Tee Topology AC'97 Trace Length Requirements......................................2-62
Daisy-Chain Topology AC'97 Trace Length Requirements ........................2-62
USB Data Signals .......................................................................................2-65
PCI Bus Layout Example ............................................................................2-67
External Circuitry for the ICH RTC..............................................................2-68
Diode Circuit Connecting RTC External Battery .........................................2-69
RTCRST External Circuit for the ICH RTC .................................................2-70
PICD[1,0] Uni-Processor Topology.............................................................3-12
PICD[1,0] Dual-Processor Topology...........................................................3-12
Test Load vs. Actual System Load .............................................................3-14
Aggressor and Victim Networks..................................................................3-17
Transmission Line Geometry: (A) Microstrip (B) Stripline...........................3-17
One Signal Layer and One Reference Plane..............................................3-21
Layer Switch with One Reference Plane ....................................................3-21
Layer Switch with Multiple Reference Planes (same type) .........................3-21
Layer Switch with Multiple Reference Planes .............................................3-22
One Layer with Multiple Reference Planes.................................................3-22
Overdrive Region and V
Rising Edge Flight Time Measurement.......................................................3-25
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Intel 820 Chipset Platform Clock Distribution .............................................4-2
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Intel 820 Chipset Clock Routing Guidelines ...............................................4-4
CK133 to DRCG Routing Diagram ...............................................................4-6
MCH to DRCG Routing Diagram ..................................................................4-7
Direct Rambus* Clock Routing Dimensions..................................................4-7
Differential Clock Routing Diagram (Section 'A', 'C', & 'D')...........................4-9
Non-Differential Clock Routing Diagram (Section 'B')...................................4-9
Termination for Direct Rambus* Clocking Signals CFM/CFM# ....................4-9
DRCG Impedance Matching Network.........................................................4-10
DRCG Layout Example...............................................................................4-11
DRCG+ Frequency Selection .....................................................................4-13
28Ω Trace Geometry ....................................................................................5-2
Microstrip and Stripline Cross-section for 28 Ω Trace ..................................5-4
7 mil Stackup (Not Routable) ........................................................................5-5
4.5 mil Stackup .............................................................................................5-5
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Intel 820 Chipset Power Delivery Example.................................................6-2
1.8V and 2.5V Power Sequencing (Schottky Diode) ....................................6-4
Use a GPO to Reduce DRCG Frequency.....................................................6-6
Power Plane Split Example...........................................................................6-7
Guardband.....................................................3-25
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