Intel VC820 - Desktop Board Motherboard Design Manual page 217

8 7
Super I/O
VCC3_3
28 VCC5_KBMS_J
D
4.7K
8,10,12,13,14,18,21,22,23,24
10,14,23,34
KBDAT
28
KBCLK
28
MDAT
28
MCLK
28
IRRX
20
C
IRTX
20
C320 C317
470PF 470PF
LPC header. For debug only.
B
J20
11,12,14 LAD3/FWH3 1 2
11,12,14 LAD2/FWH2 3 4
11,12,14 LAD1/FWH1 5 6
11,12,14 LAD0/FWH0 7 8
11,12,14 LFRAME#/FWH4 9 10
8,10,12,13,14,18,21,22,23,24PCIRST# 11 12
7,14 SIO_PCLK7 13 14
11,14 LDRQ#0 15 16
17 18
7,11 MULT1_GPIO 19 20
21 22
10,14,23,34 SERIRQ 23 24
25 26
27 28
A
8 7
6
LFRAME#/FWH4
11,12,14
LAD3/FWH3
11,12,14
LAD2/FWH2
11,12,14
LAD1/FWH1
11,12,14
LAD0/FWH0
11,12,14
LDRQ#0
11,14
PCIRST#
LPCPD#
LPC_PME#
11
SERIRQ
SIO_PCLK7
7,14
KBRST#
10,34
A20GATE
10,34
RXD0
27
TXD0
27
DSR#0
27
RTS#0
27
CTS#0
27
DTR#0
27
RI#0
27
DCD#0
27
RXD1
27
TXD1
27
DSR#1
27
RTS#1
27
CTS#1
27
DTR#1
100
27
RI#1
27
DCD#1
27
DRVDEN#1
28
DRVDEN#0
28
MTR#0
28
DS#0
28
DIR#
28
STEP#
28
WDATA#
28
WGATE#
28
HDSEL#
28
INDEX#
28
TRK#0
28
WRTPRT#
28
RDATA#
28
DSKCHG#
28
SIO_14MHZ
7
6
5 4
VCC5 VCC3_3
U17
24
LFRAME#
23
LAD3 INIT#
22
LAD2 SLCTIN#
21
LAD1 PD7
20
LAD0 PD6
LPC I/F
25
LDRQ# PD5
26
LRESET# PD4
PARALLEL PORT I/F
27
LPCPD# PD3
17
PME# PD2
30
SERIRQ PD1
SIO
29
PCI_CLK PD0
SLCT#
56
KDAT LPC47B27X PE
57
KCLK BUSY
58
MDAT ACK#
59
KYBD/MSE I/F
MCLK ERROR#
63
KBDRST ALF#
64
A20GATE STROBE#
61
IRRX2/GP34 FAN2/GP32
INFRARED I/F
62
IRTX2/GP35 FAN1/GP33
84
RXD1 FDC_PP/DDRC/GP43
85
TXD1
86
DSR1#
87
RTS1#
SERIAL PORT 1
88
CTS1#
89
DTR1#
90
RI1#
91
DCD1#
95
RXD2_IRRX
96
TXD2_IRTX
97
DSR2#
98
SERIAL PORT 2
RTS2#
99
CTS2# GP60/LED1
DTR2# GP61/LED2
92
RI2# GP27/IO_SMI#
94
DCD2# GP30/FAN_TACH2
GP31/FAN_TACH1
2
DRVDEN1 GP25/MIDI_IN
1
DRVDEN0 GP26/MIDI_OUT
3
MTR0#
5
DS0# GP10/J1B1
8
DIR# GP11/J1B2
9
STEP# GP12/J2B1
10
WDATA# GP13/J2B2
FDC I/F
11
WGATE# GP14/J1X
12
HDSEL# GP15/J1Y
13
INDEX# GP16/J2X
14
TRK0# GP17/J2Y
15
WRTPRT# GP20/P17
16
RDATA# GP21/P16
4
DSKCHG# GP22/P12
6
CLKI32 CLOCKS GP24/SYSOPT
19
CLOCKI
5 4
3 2
VCC5
PAR_INIT#
66
26
SLIN#
67
26
PDR[7:0]
PDR7
75
26
PDR6
74
PDR5
73
C309
PDR4
72
PDR3
71
PDR2 0.1UF
70
PDR1
69
PDR0
68
SLCT
77
26
PE
78
26
BUSY Place next to VREF.
79
26
ACK#
80
26
ERR#
81
26
AFD#
82
26
STB#
83
26
54 PWM2
20
55 PWM1
20
28
VCC3_3 VCC3_3
48
49
LPC_SMI#
50
11
CPU_TACH2
51
CPU_TACH1
52
MIDI_IN
46
29
MIDI_OUT
47
29
J1BUTTON1
32
29
J1BUTTON2
33
29
J2BUTTON1
34
29
J2BUTTON2
35
29
JOY1X
36
29
JOY1Y
37
29
JOY2X
38
29
JOY2Y
39
29
KEYLOCK#
41
20
42
43
45 SYSOPT
Pulldown on SYSOPT for IO address of 0x02E
4.7K
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
SUPER I/O
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630
3 2
1
VCC3_3
D
C348 C321 C313 C323
0.1UF 0.1UF 0.1UF 0.1UF 2.2UF
Place decoupling caps near each power pin.
C
B
A
REV:
3.03
DRAWN BY: PROJECT:
LAST REVISED: SHEET:
11-29-1999_14:46 14 OF 38
1