Intel VC820 - Desktop Board Motherboard Design Manual page 118

Advanced System Bus Design
propagation time on the coupled network length exceeds one half of the rise time of the aggressor's
signal. Assuming the ideal ramp on the aggressor from 0% to 100% voltage swing, and the fall
time on an unloaded coupled network, then:
An example calculation follows when the fast corner fall time is 3 V/ns and board delay is
175 ps/inch (2.1 ns/foot):
Fall time = 1.5 V÷3 V/ns = 0.5 ns
Length for Max Backward Cross-talk
= ½ * 0.5 ns * 1000 ps/ns ÷175 ps/in
= 1.43 inches
Agents on the AGTL+ bus drive signals in each direction on the network. This causes backward
cross-talk from segments on two sides of a driver. The pulses from the backward cross-talk travel
toward each other and meet and add at certain moments and positions on the bus. This can cause
the voltage (noise) from cross-talk to double.
3.3.3.1 Potential Termination Cross-Talk Problems
The use of commonly used "pull-up" resistor networks for AGTL+ termination may not be
suitable. These networks have a common power or ground pin at the extreme end of the package,
shared by 13 to 19 resistors (for 14- and 20-pin components). These packages generally have too
much inductance to maintain the voltage/current needed at each resistive load. Intel recommends
using discrete resistors, resistor networks with separate power/ground pins for each resistor, or
working with a resistor network vendor to obtain resistor networks that have acceptable
characteristics.
3-18
LengthforMaxBackwardCrosstalk
1
× allTime
-- -
F
2
= ------------------------------------------------------------------------ -
BoardDelayPerUnitLength
®
Intel 820 Chipset Design Guide