Intel VC820 - Desktop Board Motherboard Design Manual page 77

Table 2-13. Processor and 82820 MCH Connection Checklist
CPU Pin
Clock Signals
BCLK
PICCLK
Other Signals
BSEL0
BSEL1
EMI[5:1]
SLOTOCC#
TESTHI
VID[4:0]
Power
VCC
CORE
V
TT
No Connects
Reserved
NOTES:
1. For single processor designs, the AGTL+ bus can be dual-ended or single-ended termination based on
simulation results. Single-ended termination is provided by the processor.
2. This checklist supports Intel
a FMB guideline of 19.3A, and future Intel
®
Intel 820 Chipset Design Guide
UP Pin Connection (CPU0)
Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics). To reduce pin-to-pin
skew, tie host clock outputs together at the
clock driver then route to the MCH and
processor.
Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics)
100/133 MHz support: 220 Ω pull up to 3.3V,
connected to PWRGOOD logic such that a
logic low on BSEL0 negates PWRGOOD
220 Ω pull up to 3.3V, connect to CK133
SEL133/100# pin. Connect to MCH HL10 pin
via 8.2 KΩ series resistor.
Tie to GND. Zero ohm resistors are an option
instead of direct connection to GND.
Tie to GND, leave it N/C, or could be
connected to powergood logic to gate system
from powering on if no processor is present.
If used, 1 KΩ – 10 KΩ pull up to any voltage.
1 K –100 KΩ pull up to Vcc2.5
If a legacy design pulls this up to VCC
use a 1 KΩ – 10 KΩ pull up
Connect to on-board VR or VRM. For on-
board VR, 10 KΩ pull up to power-solution
compatible voltage required (usually pulled
up to input voltage of the VR). Some of these
solutions have internal pull-ups. Optional
override (jumpers, ASIC, etc.) could be used.
May also connect to system monitoring
device.
Connect to core voltage regulator. Provide
high & low frequency decoupling.
Connect to 1.5V regulator. Provide high and
low frequency decoupling.
The following pins must be left as no-
connects: A16, A47, A88, A113, A116, B12,
B20, B76, and B112.
® ®
Pentium II processors at all current speeds, Intel
®
Pentium
Layout/Routing Guidelines
1,2
(Continued)
DP Pin Connection (CPU1)
Use separate BCLK from TAP and CPU0,
or use ganged clock. Terminate as
described.
Use separate PICCLK from CPU0.
Terminate as described.
nd
Connect to 2 processor
nd
Connect to 2 processor
Implement in same manner as CPU0.
Implement in same manner as CPU0.
Implement in same manner as CPU0.
,
CORE
Implement in same manner as CPU0.
CPU0 and CPU1 should have different
VR/VRMs.
Implement in same manner as CPU0.
Implement in same manner as CPU0.
Implement in same manner as CPU0.
®
®
III processors to the current FMB guideline of 18.4A.
®
Pentium III processors to
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