Intel ® 820 Chipset Platform Clock Skews - Intel VC820 - Desktop Board Motherboard Design Manual

®
Table 4-2. Intel 820 Chipset Platform Clock Skews
Clock Symbols
See Figure 4-1
A leads C,
A leads E
(or C leads E)
A leads E
P leads F
L leads another L
(or L leads H)
I leads H
F leads I
Worst case skew
between H, L, M
and N
B leads D,
B leads G
NOTES:
1. DP Only
2. UP: MCH and CPU clock drivers are tied together to eliminate pin-to-pin skew. –175 and +175 pin-to-pin
skew only apply to DP.
3. UP Only
4. Clock drivers tied together to eliminate pin-to-pin skew.
5. The skew between any PCICLK clocks on any two inputs in the system.
6. The skew between any APIC clocks on any two inputs in the system.
7. If SSC is enabled, an additional
8. If SSC is enabled, an additional
®
Intel 820 Chipset Design Guide
Relationship
SC242 HCLK to SC242
HCLK (DP ONLY)
And -175
SC242 HCLK to MCH
HCLK (DP ONLY)
SC242 HCLK to MCH
HCLK (UP ONLY)
MCH CLK66 to AGP
graphics device
AGPCLK
PCICLK to PCICLK -500
ICH CLK66 leads ICH
+1500
PCICLK
ICH CLK66 to MCH
-250
CLK66
Worst case FWHCLK,
-500
LPCCLK, PCICLK
Processor PICCLK leads
Processor PICCLK
And -250
Processor PICCLK leads
ICH APICCLK
±
40ps must is added to the pin-to-pin skew
±
60ps must is added to the pin-to-pin skew
Skew
Pin-to-Pin Board
(ps) (ps)
Min Max Min Max
+175 -125 +125
0 0 -125 +125
0 0 -125 +125
+500 -1500 +1500
+4000 -500 +500
250 -125 +125
+500 -1500 +1500
+250 -125 +125
Clocking
Total
Notes
(ps)
Min Max
-300 +300 1, 7
-125 +125 2, 3, 7
-125 +125 4, 8
-2000 +2000
+1000 +4500
-375 +375 8
-2000 +2000 5
-375 +375 6
4-3