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Clocking is provided from the primary codec on the link via BITCLK, and is derived from a
24.576 MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator
requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller
(ICH), and any other codec present. That clock is used as the timebase for latching and driving
data.
On the Intel
AC'97 link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or
caller ID, standby power must be provided to the modem codec.
The ICH has weak pulldowns/pullups that are only enabled when the AC-Link Shut Off bit in the
ICH is set. This will keep the link from floating when the AC-link is off, or there are no codecs
present.
If the Shut-off bit is not set, it implies that there is a codec on the link. Therefore, BITCLK and
AC_SDOUT will be driven by the codec and ICH respectively. However, AC_SDIN0 and
AC_SDIN1 may not be driven. If the link is enabled, the assumption can be made that there is at
least one codec. If there is an onboard codec only (i.e., no AMR), then the unused SDIN pin should
have a weak (10 KΩ) pulldown to keep it from floating. If an AMR is used, any SDIN signal that
could be no connected (e.g., with no codec, both can be NC), then both SDIN pins must have a
10 KΩ pulldown.
Table 2-16. AC'97 SDIN Pulldown Resistors
On-board Codec Only
AMR Only
BOTH AMR and On-board Codec
NOTE: If the on-board codec can be disabled, both SDIN pins must have pulldowns. If the on-board codec can
not be disabled, only the SDIN not connected to the on-board codec requires a pulldown.
2.14.1
AC'97 Signal Quality Requirements
In a lightly loaded system (e.g., single codec down), AC'97 signal integrity should be evaluated to
confirm that the signal quality on the link is acceptable to the codec used in the design. A series
resistor at the driver and a capacitor at the codec can be implemented in order to compensate for
any signal integrity issues. The values used will be design dependent and should be verified for
correct timings. The ICH AC-link output buffers are designed to meet the AC'97 2.1 specification
with the specified load of 50pF.
2.14.2
AC'97 Motherboard Implementation
The following design considerations are provided for the implementation of an ICH0/ICH platform
using AC'97. These design guidelines have been developed to ensure maximum flexibility for
board designers while reducing the risk of board related issues. These recommendations do not
represent the only implementation or a complete checklist, but provides recommendations based on
the ICH0/ICH platform.
®
Intel
820 Chipset Design Guide
®
820 chipset platform, the ICH supports Wake on Ring from S1, S3, and S4 via the
System Solution
Pullup Requirements
Pulldown the SDIN pin that is NOT connected to the codec
Pulldown BOTH SDIN pins
Pulldown any SDIN pin that could be NC*
Layout/Routing Guidelines
2-63
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