V And 2.5V Power Sequencing (Schottky Diode) - Intel VC820 - Desktop Board Motherboard Design Manual

System Design Considerations
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The Intel
possible to use a linear regulator to regulate from 3.3VSB, however the thermal characteristics
must be considered. Additionally, a low drop out linear regulator would be necessary. If 2.5VSBYis
regulated from 3.3VSB, it is important the 3.3VSB regulator can supply enough current for all the
3.3VSB device requirements as well as the 2.5VSBY requirements.
Refer to the 1.8V power plane information for 1.8V and 2.5V power sequencing requirement.
Note: Refer to section
for more details.
Note: This regulator is required in ALL designs, however in systems that do not support STR, the 2.5V
rail would be powered from either the 3.3V or 5V core well.
1.8V
The 1.8V plane powers the MCH core, the ICH hub interface I/O buffers and the RDRAM
termination resistors. This power plane has a total power requirement of approximately 1.7A. The
1.8V plane should be decoupled with a 0.1 uF and a 0.01 uF chip capacitor at each corner of the
MCH and with a single 1 uF and 0.1 uF capacitor at the ICH. Additionally, the 1.8V plane should
be decoupled at the RDRAM termination as shown in
Guidelines" on page
Power MUST NOT be applied to the RDRAM termination resistors (Vterm) prior to applying
power to the RDRAM Core (2.5VSBY in this design). This can be guaranteed by placing a
Schottky diode between 1.8V and 2.5V as shown in
Figure 6-2. 1.8V and 2.5V Power Sequencing (Schottky Diode)
Note: This regulator is required in ALL designs.
VDDQ
The VDDQ plane is used to power the MCH AGP interface and the graphics component AGP
interface. Refer to the AGP Interface Specification Revision 2.0 (http://www.agpforum.org).
Note: This regulator is required in ALL designs (unless the design does not support 1.5V AGP, and
therefore does not support 4X AGP).
For the consideration of component long term reliability, the following power sequence is required
while the AGP interface of MCH is running at 3.3V. If the AGP interface is running at 1.5V, the
following power sequence requirement is no longer applicable. The power sequence requirements
are:
1. During the power-up sequence, the 1.8V must ramp up to 1.0V BEFORE 3.3V ramps up to
2.2V
2. During the power-down sequence, the 1.8V CAN NOT ramp below 1.0V BEFORE 3.3V
ramps below 2.2V
3. The same power sequence recommendation also applies to the entrance and exit of S3 state,
since MCH power is completely off during the S3 state.
6-4
820 Chipset Reference Board is using a switching regulator from 5V Dual. It may be
Section 6.1.3, "64/72Mbit RDRAM Excessive Power Consumption" on page 6-5
2-8.
Section 2.6.2, "Direct Rambus* Layout
Figure 6-2.
1.8V
2.5V
Intel
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820 Chipset Design Guide