Unused Outputs; Decoupling Recommendation For Ck133 And Drcg; Drcg Frequency Selection And The Drcg; Drcg Frequency Selection Table And Jitter Specification - Intel VC820 - Desktop Board Motherboard Design Manual

Clocking
4.6

Unused Outputs

All unused clock outputs must be tied to ground through a series resistor approximately the
impedance of the output buffer (shown below.) The intent of these resistors is to terminate the
unused outputs to eliminate EMI.
Table 4-6. Unused Output Termination
CPU, CPU_Div2, IOAPIC
48 MHz, REF
PCI, 3V66
4.7

Decoupling Recommendation for CK133 and DRCG

Some CK133 vendors may integrate the XTAL_IN and XTAL_OUT frequency adjust capacitors.
However, pads should be placed on the board for these external capacitors for testing/debug.
To further reduce jitter and voltage supply noise, the addition of a ferrite filter with 2 caps (10 uF
and 0.1 uF) on both the 2.5V and 3.3V planes close to the clock devices is recommended. This
applies to both DRCG and CK133.
4.8

DRCG Frequency Selection and the DRCG+

4.8.1

DRCG Frequency Selection Table and Jitter Specification

To allow additional flexibility in board design, Intel has enabled a variation of the DRCG labeled
the DRCG+. The device has the same specifications, pinout and form-factor as the existing DRCG
device document. There are two modifications made to the DRCG+.
1. The DRCG+ Mult[0:1] select table has changed to modify two of the multiplier ratios. The
DRCG+ will support 133/356 MHz using 66 MHZ DRCG+ input clock and a 16/3 multiplier.
An additional 9/2 multiplier allows 133/300 MHz (not supported by the Intel
Support for 300 MHz and 400 MHz memory bus is unchanged. The following table lists the

DRCG Ratio.

Table 4-7. DRCG Ratio
Mult[0:1]
4-12
Buffer Name
DRCG DRCG+
0:0 4:1
0:1 6:1
1:0 8:3
1:1 8:1
Impedance
VCC Range (V)
(Ohms)
2.375 - 2.625 13.5 - 45
3.135 - 3.465 20 - 60
3.135 - 3.465 12 - 55
9:2
6:1
16:3
8:1
If Unused Output
Termination to VSS
30 Ohms
40 Ohms
33 Ohms
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820 chipset).
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Intel 820 Chipset Design Guide