Intel VC820 - Desktop Board Motherboard Design Manual page 103

Term
Network
Network
Length
Overdrive
Region
Overshoot
Pad
Pin
Ringback
Settling Limit
Setup Window
Simultaneous
Switching
Output (SSO)
Effects
Stub
Test Load
Trunk
Undershoot
Victim
V Guardband A guardband (∆V
REF
®
Intel 820 Chipset Design Guide
Definition
The trace of a Printed Circuit Board (PCB) that completes an electrical
connection between two or more components.
The distance between extreme bus agents on the network and does not include
the distance connecting the end bus agents to the termination resistors.
Is the voltage range, at a receiver, located above and below V
integrity analysis. See the Intel
more details.
Maximum voltage allowed for a signal at the processor core pad. See each
processor's datasheet for overshoot specification.
A feature of a semiconductor die contained within an internal logic package on
the S.E.C cartridge substrate used to connect the die to the package bond wires.
A pad is only observable in simulation.
A feature of a logic package contained within the S.E.C. cartridge used to
connect the package to an internal substrate trace.
Ringback is the voltage that a signal rings back to after achieving its maximum
absolute value. Ringback may be due to reflections, driver oscillations, etc. See
the respective processor's datasheet for ringback specification.
Defines the maximum amount of ringing at the receiving pin that a signal must
reach before its next transition. See the respective processor's datasheet for
settling limit specification.
Is the time between the beginning of Setup to Clock (T
a valid clock edge. This window may be different for each type of bus agent in
the system.
Refers to the difference in electrical timing parameters and degradation in signal
quality caused by multiple signal outputs simultaneously switching voltage
levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-
to-high) or in the same direction (e.g., high-to-low). These are respectively
called odd-mode switching and even-mode switching. This simultaneous
switching of multiple outputs creates higher current swings that may cause
additional propagation delay (or "pushout"), or a decrease in propagation delay
(or "pull-in"). These SSO effects may impact the setup and/or hold times and are
not always taken into account by simulations. System timing budgets should
include margin for SSO effects.
The branch from the trunk terminating at the pad of an agent.
Intel uses a 50 Ω test load for specifying its components.
The main connection, excluding interconnect branches, terminating at agent
pads.
Maximum voltage allowed for a signal to extend below V
pad. See the respective processor's datasheet for undershoot specifications.
A network that receives a coupled cross-talk signal from another network is
called the victim network.
) defined above and below V
REF
model accounting for noise such as cross-talk, V
Advanced System Bus Design
®
Pentium II Processor Developer's Manual for
®
SU_MIN
to provide a more realistic
REF
noise, and V
TT
for signal
REF
) and the arrival of
at the processor core
SS
noise.
REF
3-3