Intel VC820 - Desktop Board Motherboard Design Manual page 175

8 7
Super I/O
VCC3_3
26 VCC5_KBMS_J
D
4.7K
1 2 3 4
8 7 6 5 6,8,10,11,12,16,19,20,21,22
8,12,21,32
KBDAT
26
KBCLK
26
MDAT
26
MCLK
26
IRRX
18
C
IRTX
18
C320 C317
470PF 470PF
LPC header. For debug only.
B
J20
9,10,12 LAD3/FWH3 1 2
9,10,12 LAD2/FWH2 3 4
9,10,12 LAD1/FWH1 5 6
9,10,12 LAD0/FWH0 7 8
9,10,12 LFRAME#/FWH4 9 10
6,8,10,11,12,16,19,20,21,22 PCIRST# 11 12
5,12 SIO_PCLK7 13 14
9,12 LDRQ#0 15 16
17 18
5,9 MULT1_GPIO 19 20
21 22
8,12,21,32 SERIRQ 23 24
25 26
27 28
A
8 7
6
LFRAME#/FWH4
24
9,10,12
LAD3/FWH3
23
9,10,12
LAD2/FWH2
22
9,10,12
LAD1/FWH1
21
9,10,12
LAD0/FWH0
20
9,10,12
LDRQ#0
25
9,12
PCIRST#
26
LPCPD#
27
LPC_PME#
17
9
SERIRQ
30
SIO_PCLK7
29
5,12
56
57
58
59
KBRST#
63
8,32
A20GATE
64
8,32
61
62
RXD0 84
25
TXD0 85
25
DSR#0
86
25
RTS#0 87
25
CTS#0
88
25
DTR#0
89
25
RI#0
90
25
DCD#0
91
25
RXD1
95
25
TXD1
96
25
DSR#1
97
25
RTS#1
98
25
CTS#1
99
25
DTR#1
100
25
RI#1
92
25
DCD#1
94
25
DRVDEN#1
26
DRVDEN#0
26
MTR#0
26
DS#0
26
DIR#
26
STEP#
26
WDATA#
10
26
WGATE#
11
26
HDSEL#
12
26
INDEX#
13
26
TRK#0
14
26
WRTPRT#
15
26
RDATA#
16
26
DSKCHG#
26
SIO_14MHZ
19
5
6
5 4
VCC5 VCC3_3
U17
LFRAME#
LAD3 INIT#
LAD2 SLCTIN#
LAD1 PD7
LAD0 PD6
LPC I/F
LDRQ# PD5
LRESET# PD4
PARALLEL PORT I/F
LPCPD# PD3
PME# PD2
SERIRQ PD1
SIO
PCI_CLK PD0
SLCT#
KDAT LPC47B27X PE
KCLK BUSY
MDAT ACK#
KYBD/MSE I/F
MCLK ERROR#
KBDRST ALF#
A20GATE STROBE#
IRRX2/GP34 FAN2/GP32
INFRARED I/F
IRTX2/GP35 FAN1/GP33
RXD1 FDC_PP/DDRC/GP43
TXD1
DSR1#
RTS1#
SERIAL PORT 1
CTS1#
DTR1#
RI1#
DCD1#
RXD2_IRRX
TXD2_IRTX
DSR2#
SERIAL PORT 2
RTS2#
CTS2# GP60/LED1
DTR2# GP61/LED2
RI2# GP27/IO_SMI#
DCD2# GP30/FAN_TACH2
GP31/FAN_TACH1
2
DRVDEN1 GP25/MIDI_IN
1
DRVDEN0 GP26/MIDI_OUT
3
MTR0#
5
DS0# GP10/J1B1
8
DIR# GP11/J1B2
9
STEP# GP12/J2B1
WDATA# GP13/J2B2
FDC I/F
WGATE# GP14/J1X
HDSEL# GP15/J1Y
INDEX# GP16/J2X
TRK0# GP17/J2Y
WRTPRT# GP20/P17
RDATA# GP21/P16
4
DSKCHG# GP22/P12
6
CLKI32 CLOCKS GP24/SYSOPT
CLOCKI
5 4
3 2
VCC5
PAR_INIT#
66
24
SLIN#
67
24
PDR[7:0]
PDR7
75
24
PDR6
74
PDR5
73
C309
PDR4
72
PDR3
71
PDR2 0.1UF
70
PDR1
69
PDR0
68
SLCT
77
24
PE
78
24
BUSY Place next to VREF.
79
24
ACK#
80
24
ERR#
81
24
AFD#
82
24
STB#
83
24
54 PWM2
18
55 PWM1
18
28
VCC3_3
48
49
LPC_SMI#
50
9
TACH2
51
18
CPU_TACH1
52
MIDI_IN
46
27
MIDI_OUT
47
27
J1BUTTON1
32
27
J1BUTTON2
33
27
J2BUTTON1
34
27
J2BUTTON2
35
27
JOY1X
36
27
JOY1Y
37
27
JOY2X
38
27
JOY2Y
39
27
KEYLOCK#
41
18
42
43
45 SYSOPT
Pulldown on SYSOPT for IO address of 0x02E
4.7K
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
SUPER I/O
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630
3 2
1
VCC3_3
D
1
C348 C321 C313 C323
2
0.1UF 0.1UF 0.1UF 0.1UF 2.2UF
Place decoupling caps near each power pin.
C
B
A
REV:
1.01
DRAWN BY: PROJECT:
LAST REVISED: SHEET:
11-18-1999_10:46 12 OF 36
1