Agp 2.0 Vref Generation & Distribution - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
During 3.3V AGP 2.0 operation, V
operation, Vref must be 0.5VDDQ. This requires a flexible voltage divider for V
methods of accomplishing this exist, and one such example is shown in
Figure 2-32. AGP 2.0 VREF Generation & Distribution
1.5V AGP
Card
3.3V AGP
Card
VDDQ
AGP
Device
GND
The flexible V
generated V
Usage of the source generated V
issue which is beyond the scope of this document.
2-40
REF
+12V
O Note: R7 is the same resistor seen in
AGP VDDQ Generation Example Circuit
R7
1K
TYPEDET#
VrefGC
VDDQ
AGP
REF
Device
GND
VrefCG
The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.
+12V
O
Note: R7 is the same resistor seen in AGP
VDDQ Generation Example Circuit Figure
R7
1K
TYPEDET#
VrefGC
REF
VrefCG
The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.
divider shown in Figure 2-32
REF
(for 3.3V add-in cards) and the source generated V
REF
at the receiver is optional and is a product implementation
REF
must be 0.4VDDQ. However, during 1.5V AGP 2.0
Figure (R1)
R9
300
1%
R11
200
1%
U6
mosfet
Place C10 close to the MCH
R9
(R1)
300
1%
R11
200
1%
U6
mosfet
0.1uF
C10
Place C10 close to the MCH
uses a FET switch to switch between the locally
. Various
REF
Figure 2-32.
VDDQ
500pF
C8
R6
1K
VDDQ
MCH
REF
0.1uF
GND
R2
C10
1K
500pF
C9
VDDQ
R6
1K
VDDQ
MCH
REF
GND
R2
1K
500pF
C9
(for 1.5V add-in cards).
REF
®
Intel 820 Chipset Design Guide
R5
82
R4
82
500pF
C8
R5
82
R4
82