Intel VC820 - Desktop Board Motherboard Design Manual page 8

Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
6-1
6-2
viii
®
Intel 820 Chipset Platform Bandwidth Summary ........................................1-4
AGP 2X Data/Strobe Association .................................................................2-6
Placement Guidelines for Motherboard Routing Lengths .............................2-9
Copper Tab Area Calculation .....................................................................2-15
RSL Routing Layer Requirements ..............................................................2-21
Line Matching and Via Compensation Example .........................................2-24
Signal List ...................................................................................................2-28
AGP 2.0 Data/Strobe Associations.............................................................2-33
AGP 2.0 Routing Summary ........................................................................2-35
TYPDET#/VDDQ Relationship ...................................................................2-38
Connector/Add-in Card Interoperability ......................................................2-42
Voltage/Data Rate Interoperability..............................................................2-42
Segment Descriptions and Lengths for
Processor and 82820 MCH Connection Checklist......................................2-49
Bus Request Connection Scheme for DP Intel
ICH Codec Options.....................................................................................2-61
AC'97 SDIN Pulldown Resistors .................................................................2-63
AGTL+ Parameters for Example Calculations ..............................................3-6
Example T Calculations for 133 MHz Bus .......................................3-7
FLT_MAX
Example T Calculations (Frequency Independent)...........................3-8
FLT_MIN
Trace Width Space Guidelines ...................................................................3-11
Host Clock Routing .....................................................................................3-12
®
Intel 820 Chipset Platform System Clocks..................................................4-1
®
Intel 820 Chipset Platform Clock Skews.....................................................4-3
®
Intel 820 Chipset Platform System Clock Cross-Reference .......................4-5
Placement Guidelines for Motherboard Routing Lengths .............................4-8
External DRCG Component Values ...........................................................4-10
Unused Output Termination........................................................................4-12
DRCG Ratio................................................................................................4-12
28Ω Stackup Examples ................................................................................5-3
3D Field Solver vs ZCALC............................................................................5-4
®
Intel 820 Chipset Component Thermal Design Power................................6-7
Glue Chip 3 Vendors ....................................................................................6-8
Figure 2-36 ...................................2-46
®
820 Chipset Designs.......2-52
®
Intel 820 Chipset Design Guide