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Intel 8XC251SA Hardware Description

Intel 8XC251SA Hardware Description

Addendum to the 8xc251sa, 8xc251sb, 8xc251sp, 8xc251sq, user’s manual
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8xC251TB, 8xC251TQ,
Hardware Description
Addendum to the 8xC251SA, 8xC251SB,
8xC251SP, 8xC251SQ, User's Manual
Release Date: December 2003
Order Number: 273138-002
The 8xC251Tx may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Such errata are not covered by
Intel's warranty. Current characterized errata are available on request.

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Summary of Contents for Intel 8XC251SA

  • Page 1 Release Date: December 2003 Order Number: 273138-002 The 8xC251Tx may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are not covered by Intel's warranty. Current characterized errata are available on request.
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any...
  • Page 3 REVISION HISTORY: Date November 1997 December 2003 273138-002 8xC251Tx Hardware Description Revision Initial release of this document Removed references to 8XC251TA, 8XC251TP December 2003 Description...
  • Page 4 8xC251Tx Hardware Description December 2003 273138-002...

  • Page 5: Table Of Contents

    8xC251TB, 8xC251TQ Hardware Description Addendum to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ, User’s Manual 1.0 INTRODUCTION TO THE 8xC251Tx Comparing the 8xC251Tx and 8xC251Sx ... 1 2.0 SIGNAL SUMMARY 3.0 THE SECOND SERIAL I/O PORT Overview... 7 Special Function Register Definitions ... 9 3.2.1...
  • Page 6 8xC251Tx Hardware Description December 2003 273138-002...

  • Page 7: Introduction To The 8Xc251Tx

    This document addresses the differences between the two members of the MCS 251 microcontroller family. For a detailed description of the MCS 251 microcontroller core and standard peripherals shared by both the 8xC251Sx and 8xC251Tx, please refer to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual (272795).

  • Page 8: Signal Summary

    8xC251Tx Hardware Description 2.0 SIGNAL SUMMARY Address & Data Name PLCC AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15P2.7 P3.7/RD#/A16 P1.7/CEX4/A17/WCLK Processor Control Name PLCC P3.2/INT0# P3.3/INT1# XTAL1 XTAL2 NOTE: Pins in this font indicate functions associated with the second serial I/O port. Table 1.

  • Page 9: Ie1

    Address Line 17. Output to memory as the 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4, "Device Configuration," of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual (272795). See also RD# and PSEN#.
  • Page 10 8xC251Tx Hardware Description Table 2. 8xC251Tx Signal Descriptions (Sheet 2 of 3) Signal Type Name P3.0 Port 3. This is an 8 bit, bidirectional I/O port with internal pullups P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 PSEN# Program Store Enable. Read signal output to external memory. Asserted for the address range specified by the configuration byte UCONFIG0, bits RD1:0.
  • Page 11 Table 2. 8xC251Tx Signal Descriptions (Sheet 3 of 3) Signal Type Name Secondary Supply Voltage 2. This supply voltage connection is pro- vided to reduce power supply noise. Connection of this spin to the +5V supply voltage is recommended. However, when using the ZX3 as a pin for pin replacement for the 8XC51FX, V nected without loss of compatibility (Not available on DIP).

  • Page 12: Scon1

    8xC251Tx Hardware Description Table 3. Special Function Register (SFR) Map CH00000 00000000 00000000 00000000 CCON CMOD 00x00000 00xxx000 PSW1 00000000 00000000 T2CON T2MOD 00000000 xxxxxx00 IPL0 SADEN x0000000 00000000 11111111 xxxxxxx0 SADDR 00000000 00000000 11111111 SCON SBUF 00000000 xxxxxxxx 11111111 TCON000 TMOD 00000...

  • Page 13: The Second Serial I/O Port

    (SFRs) associated with the second serial port. Detailed operation and programming of the serial I/O ports can be obtained from Chapter 10 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcon- troller User’s Manual (272795). All the SFRs and control bits for the standard serial I/O port in both the 8xC251Sx and 8xC251Tx have an equivalent in the second serial I/O port.

  • Page 14: Table 5. Second Serial I/O Port Special Function Registers

    IPL1 and IPH1 registers, respectively. The second serial I/O port is last in the interrupt polling sequence (see Chapter 6 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual (272795) for details of the interrupt system). The second serial I/O port's Interrupt Service Routine Vector Address is FF:0043H.

  • Page 15: Special Function Register Definitions

    Special Function Register Definitions The following describes the special function registers associated with the second serial I/O port and their bit definitions. 3.2.1 SCON1 Address: 9AH Reset Value: 0000 0000B Table 6. SCON1 Special Function Register Definitions Bit Number Mnemonic FE1SM0 Framing Error Bit 1: To Select this function, set the SMOD0 bit in the BGCON register.

  • Page 16: Table 7. Bgcon Special Function Register Definitions

    8xC251Tx Hardware Description 3.2.2 SBUF1 Address: 9BH Reset Value: xxxx xxxxB To send serial data, software writes a byte to SBUF1 and to receive serial data, software reads from SBUF1. 3.2.3 SADDR1 Address: AAH Reset Value: 0000 0000B Slave Individual Address Register1 (SADDR1) contains the device’s individual address for multiprocessor communications.

  • Page 17: Iph1

    3.2.6 Address: B1H Reset Value: xxxx xxx0B Table 8. IE1 Special Function Register Definitions Bit Mne- Bit Number monic 7 - 1 Reserved Second serial I/O port Interrupt Enable: Setting this bit enables the second serial I/O port interrupt 3.2.7 IPH1 Address: B3H Reset Value: xxxx xxx0B...

  • Page 18: Extended Data Float Timing

    EDF#. In the 8xC251Sx, Bit 3 is defined as WSB. The implications of this change are discussed below. Refer to Chapter 4 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual (272795) for details of the device configuration for the 8xC251Sx. The information in that chapter is valid for the 8xC251Tx with the exception of the change noted in this section.

  • Page 19: Table 13. Summary Of The Edf# And Wsb#[1:0] Configuration Options

    Table 13 shows the effect of programming EDF# and WSB#[1:0] on the extended data float timing feature as well as the insertion of wait states for region 01:. It should be noted that enabling the extended data float timing allows region 01: to have 1 or 3 wait states inserted (depending on WSB#[1:0]) but not 0 or 2 wait states.

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