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R
14.8.3.
Hub Interface
Pin Name
HLVREF
PSWING
HLZCOMP
14.8.4.
Graphics Interfaces
14.8.4.1. LVDS
Pin Name
LIBG
YAP[3:0]/YAM[3:0]
YBP[3:0]/YBM[3:0]
CLKAP/CLKAM
CLKBP/CLKBM
LVREFH, LVREFL,
LVBG
14.8.4.2. AGP/DVO
Pin Name
DVORCOMP
GVREF
GAD[28:25]/DVOCD[11:6]
GCBE#3/DVOCD5
GAD[23:19]/DVO[4:0]
GADSTB1/DVOCCLK
GADSTB#/DVOCCLK#
GAD17/DVOCHSYNC
GAD16/DVOCVSYNC
GAD18/DVOCBLANK#
GAD31/DVOCFLDSTL
®
®
Intel
852GME, Intel
852GMV and Intel
System
Pull-up/Pull-down
See Section 14.9.9.
See Section 14.9.9.
48.7
1% pull-up to VCC
System
Pull-up/Pull-down
1.5 k 1% pull-down to gnd
System
Pull-up/Pull-down
40.2
1% pull-down to gnd
1 k 1% pull-up to Vcc1_5
1 k 1% pull-down to gnd
100 k pull-down to gnd
®
852PM Chipset Platforms Design Guide
Platform Design Checklist
Notes
Signal voltage level = 0.35 V ± 8%.
Signal voltage level = 0.8 V ± 8%.
Notes
If any of these LVDS data pairs are unused, they can
be left as "no connect."
If any of these LVDS clock pairs are not used, they
can be left as "no connect."
These signals should be left as NC.
Notes
Trace should be 10-mil wide with 20-mil
spacing.
Signal voltage level = 1/2 of Vcc1_5. Need 0.1
µF cap at pin.
If unused, these signals can be left as NC.
Pull-down resistor required only if signal is
unused (10 k-100 k). It is up to DVO device to
drive this signal.
251
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