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A
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
+V3.3ALWAYS
C7A2
0.1UF
U7A3
1
44
PWR_PWROK
2
74AHC1G08
20
V1.5_PWRGD
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
+V3.3ALWAYS
4
C7B2
0.1UF
1
43
DDR_VR_PWRGD
2
74AHC1G08
21
V5A_PWRGD
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
20,21,23,26,31,33,34,35,36,38,40,41,44,48
+V3.3S
Step 3 - Power Good
R4B7
C5N3
10K
0.1UF
40
ON_BOARD_VR_PWRGD
INTERPOSER_PRES#
3
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
14
U4B3C
10
INTERPOSER_PRES
74HC00
8
9
7
R5N7
OFF_BOARD_VR_PWRGD
100K
VR Interposer
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
+V3.3S
2
R1J1
R2Y1
R1Y4
330
330
330
VID5_LED
VID4_LED VID3_LED
DS1J1
DS2J3
DS2J4
GREEN
GREEN
GREEN
J4C1
VR_VID5
1
VR_VID4
3
VR_VID3
5
OFF_BOARD_VR_ON
7
OFF_BOARD_VR_PWRGD
9
11
3,40
H_PROCHOT#
13
INTERPOSER_PRES#
15
17
19
21
23
1
25
27
29
31
33
35
37
39
+V3.3S
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
20x2_Header
A
B
Step 1 - Power OK
C7A4
0.1UF
U7A6
MAIN_PWROK
4
1
4
PM_PWROK 19,21,25,32,37
MAIN2_PWROK
2
74AHC1G08
U7B1
4
+V3.3ALWAYS
14
U4B3A
14
U4B3B
1
PWRGD1
74HC00
3
4
74HC00
2
6
5
7
7
+V3.3ALWAYS
14
U4B3D
13
PWRGD2
74HC00
11
12
7
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
3
H_VID5
R1Y3
R1Y2
R1Y1
330
330
330
CON3_HDR
VID2_LED
VID1_LED
VID0_LED
DS1J2
DS1J3
DS1J4
GREEN
GREEN
GREEN
VR_VID2
2
VR_VID1
4
VR_VID0
6
8
PM_STPCPU# 6,19,37,40
10
PM_DPRSLPVR 19,37,40
SMB_DATA_VR
12
SMB_CLK_VR
14
16
NO_STUFF_0
R4C17
18
20
22
NO_STUFF_0
R4C18
24
26
28
30
IMVP-V_NET7 40
32
(Bootselect_5V)
34
36
38
40
+V5S
8,15,16,17,18,20,23,24,25,27,34,35,40,44,47
B
C
32
VR_SHUT_DOWN#
VR_PWRGD 37
15,18,19,20,23,27,30,32,35,37,38,43,44
40,42
GMCH_VCORE_PWRGD
+V3.3S
VR_VID5
40
4
R1H4
1K
J1H2
VR_VID5
VID5 Setting
J1H2
Processor Control
1-2 (Default)
Logic "0"
2-3
Logic "1"
1-X
4
CON3_HDR
CON3_HDR
CON3_HDR
CON3_HDR
CON3_HDR
SMB_DATA_S 6,8,11,12,16,18
47
47
SMB_CLK_S 6,8,11,12,16,18
47
47
47
C
D
Step 2 - VR ON
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
C5B10
0.1UF
U5B4
INTERPOSER_PRES#
1
4
74AHC1G08
2
OFF_BOARD_VR_ON
+V3.3S
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
C5B8
0.1uF
10%
U5B3
1
VR_ON
32,37,40,42
4
74AHC1G08
2
DELAYED_VIDPWRGD 40
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
+V3.3
C7B1
U7A5
0.1UF
1
R2G11
IMVP_PWRGD_D
4
74AHC1G08
2
10K
IMVP_PWRGD 7,41
VID Settings
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
H_VID[4:0]
R1F1
1K
1K
H_VID0
H_VID1
H_VID2
J1G1
H_VID3
J1G2
H_VID4
J1G3
STRAP_VID0
0
J1G4
STRAP_VID1
1
J1H1
STRAP_VID2
2
STRAP_VID3
3
STRAP_VID4
BX
2
1
J1F1
STRAP_VID4
STRAP_VID3
R1F7
STRAP_VID2
8.2K
STRAP_VID1
STRAP_VID0
Title
Processor VR Interposer Support & Power Circuitry
Size
Project:
A
Date:
Friday, May 21, 2004
D
E
+V3.3S
R5N9
C5C1
2.2k
0.1UF
U5C1
1
4
ON_BOARD_VR_ON 40
74AHC1G08
2
+V3.3S
R3G10
10K
VR_PWRGD_CK408# 6
3
Q2G1
1
2N3904
2
+V3.3S
Note: J1F1 enables
Manual VID strapping
R1F3
With pin 13 high, B input goes to C
1K
output. With pin 13 low, A input goes
to C output.
U1F1
3
2
A0
C0
VR_VID0 34,40
7
6
VR_VID1 34,40
A1
C1
11
10
VR_VID2 34,40
A2
C2
17
16
VR_VID3 34,40
A3
C3
21
20
A4
C4
VR_VID4 34,40
4
5
B0
D0
8
9
B1
D1
14
15
B2
D2
+V5S
18
19
B3
D3
22
23
B4
D4
BE#
1
24
BE#
VCC
13
12
BX
GND
C1F2
0.01UF
Bus_Switch_74CBT3383
R1E1
1K
For EVMC use, J1F1 is to be jumpered and J1G1,
J1G2, J1G3, J1G4, J1H1 need to be jumpered 1-2
Document Number
Sheet
39
of
46
E
4
3
2
8,15,16,17,18,20,
1
Rev
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