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R
Table 42. DVO Enabled Routing Guideline Summary
Signal
DVO Timing
Domain
For DVO module case, the simulation model is the same as Figure 45 and the routing guideline is the
same as in
Table 42; each strobe pair must be separated from other signals by at least 12 mils. For multiplexed
design, more conservative length mismatch (± 0.1 inches) is adopted.
7.4.1.1.
Generic Connector Model
Figure 46 shows the generic connector model used in simulation for flexible DVO implementation.
This is only for reference. Actual connector may have different parasitic values. Designs using this
approach need to be simulated first.
Figure 46. Generic Module Connector Parasitic Model
7.5.
DVO GMBUS and DDC Interface Considerations
The GMCH DVOB and/or DVOC port controls the video front-end devices via the GMBUS (I2C)
interface. DDCADATA and DDCACLK should be connected to the CRT connector. The GMBUS
should be connected to the DVO device, as required by the specifications for those devices. The
protocol and bus may be used to configure registers in the TV encoder, TMDS transmitter, or any other
external DVI device. The GMCH also has an option to utilize the DDCPCLK and DDCPDATA to
collect EDID (Extended Display Identification) from a digital display panel.
Pull-ups (or pull-ups with the appropriate value derived from simulating the signal) typically ranging
from 2.2 k to 10 k are required on each of these signals.
The following GMCH signal groups list the five possible GMBUS pairs.
®
®
Intel
852GME, Intel
852GMV and Intel
Maximum
Trace Width
Length
L1=4 in
4 mils
L2=2 in
Motherboard
20mΩ
C
2.21 pF
1
®
852PM Chipset Platforms Design Guide
Integrated Graphics Display Port
Trace Spacing
8 mils
R
L
2.5nH
C
2
Length
Notes
Mismatch
± 100 mils
Module
2.21 pF
125
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