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Figure 62. Example Speaker Circuit
10.4.
USB 2.0 Guidelines and Recommendations
10.4.1.
Layout Guidelines
10.4.1.1. General Routing and Placement
Use the following general routing and placement guidelines when laying out a new design. These
guidelines will help to minimize signal quality and EMI problems. The USB 2.0 validation efforts
focused on a four-layer motherboard where the first layer is a signal layer, the second plane is power,
the third plane is ground and the fourth is a signal layer. This results in the placement of most of the
routing on the fourth plane (closest to the ground plane), allowing a higher component density on the
first plane.
1. Place the ICH4-M and major components on the un-routed board first. With minimum trace
lengths, route high-speed clock, periodic signals, and USB 2.0 differential pairs first. Maintain
maximum possible distance between high-speed clocks/periodic signals to USB 2.0 differential
pairs and any connector leaving the PCB (i.e. I/O connectors, control and signal headers, or power
connectors).
2. USB 2.0 signals should be ground referenced (on recommended stack-up this would be the
bottom signal layer).
3. Route USB 2.0 signals using a minimum of vias and corners. This reduces reflections and
impedance changes.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal by minimizing impedance discontinuities. (As shown
in Figure 62).
5. Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices or
ICs that use and/or duplicate clocks.
6. Stubs on high-speed USB signals should be avoided, as stubs will cause signal reflections and
affect signal quality. If a stub is unavoidable in the design, the sum of all stubs for a particular
signal line should not exceed 200 mils.
7. Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing
over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and
radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0
®
®
Intel
852GME, Intel
852GMV and Intel
R Value is
Implementation
Intel
®
ICH4-M
SPKR
Integrated
Pull-down
9K - 50KΩ
®
852PM Chipset Platforms Design Guide
VCC3_3
Stuff Jumper to Disable
Specific
Timeout Feature
(No Reboot)
I/O Subsystem
Effective Impedance
Due to Speaker and
Codec Circuit
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