Table of Contents
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A
H_A#16
N5
H_A#15
N4
H_A#14
N2
H_A#13
M1
H_A#12
N1
H_A#11
M4
H_A#10
M3
H_A#9
H_A#8
M6
H_A#7
H_A#6
4
K1
H_A#5
H_A#4
K4
8
H_A#[16:3]
H_A#3
K2
8
H_ADSTB#0
H_REQ#4
H3
H_REQ#3
H_REQ#2
H_REQ#1
K5
H_REQ#0
8
H_REQ#[4:0]
TP_CPU_A35#
AB1
TP_CPU_A34#
Y1
TP_CPU_A33#
W2
TP_CPU_A32#
V3
8
H_A#[31:17]
H_A#31
U4
H_A#30
H_A#29
W1
H_A#28
R6
H_A#27
V2
H_A#26
H_A#25
U3
H_A#24
P6
H_A#23
U1
H_A#22
3
H_A#21
R3
H_A#20
P4
H_A#19
P3
H_A#18
R2
H_A#17
R5
8
H_ADSTB#1
Note: Host Clock
terminations are at
6
CLK_CPU_BCLK
the source (CK408)
R2F1
6
CLK_CPU_BCLK#
R2F2
6
CLK_ITP_CPU
R3F1
2
6
CLK_ITP_CPU#
R3F2
18
H_A20M#
18
H_FERR#
18
H_IGNNE#
18,37
H_INTR
18,37
H_NMI
18,37
H_SMI#
18,37
H_STPCLK#
5
H_THERMDA
5
H_THERMDC
39,40
H_PROCHOT#
+VCC_IMVP
4,5,9,10,18,20,40,41,47,48
RP4C1C
56
6
RP4C1B
56
7
RP3C1C
56
6
RP3C1B
56
7
RP3C1D
56
5
RP4C1A
56
8
1
40
H_VIDPWRGD
39
H_VID5
40
+VCC_VID
R2R1
0
C2R1
0.1uF
<NO_STUFF>
VCC_VID_CPU_D
A
B
U2E1B
H_ADS#
G1
A16#
ADS#
TP_CPU_AP0#
AC1
A15#
AP0#
TP_CPU_AP1#
V5
A14#
AP1#
TP_CPU_BINIT#
AA3
A13#
BINIT#
G2
H_BNR#
A12#
BNR#
D2
A11#
BPRI#
H_BPRI# 8
A10#
L2
A9#
TP_CPU_DP3#
L25
A8#
DP3#
TP_CPU_DP2#
L3
K26
A7#
DP2#
TP_CPU_DP1#
K25
A6#
DP1#
TP_CPU_DP0#
L6
J26
A5#
DP0#
E2
H_DEFER# 8
A4#
DEFER#
H2
H_DRDY# 8
A3#
DRDY#
L5
H5
H_DBSY# 8
ADSTB0#
DBSY#
REQ4#
J3
REQ3#
H_BR3#
RP2D1B
J4
U6
2
REQ2#
TESTHI8
H_BR2#
RP2D1D
W4
4
REQ1#
TESTHI9
H_BR1#
RP2D1C
J1
Y3
3
REQ0#
TESTHI10
H6
BR0#
A35#
4,5,9,10,18,20,40,41,47,48
A34#
H_IERR_PU#
AC3
A33#
IERR#
A32#
A31#
T5
W5
A30#
INIT#
H_INIT#
A29#
4,5,9,10,18,20,40,41,47,48
A28#
G4
H_LOCK# 8
A27#
LOCK#
T4
A26#
A25#
TP_CPU_MCERR#
V6
A24#
MCERR#
A23#
T2
A22#
AB25
A21#
RESET#
H_RS#2
F4
A20#
RS2#
H_RS#1
G5
A19#
RS1#
H_RS#0
F1
A18#
RS0#
TP_CPU_RSP#
T1
AB2
A17#
RSP#
J6
ADSTB1#
TRDY#
F3
HIT#
E3
HITM#
Processor-MobilSkt
49.9_1%
4,5,9,10,18,20,40,41,47,48
49.9_1%
U2E1C
AF22
BCLK0
49.9_1%
AF23
BCLK1
AC26
ITP_CLK0
AD26
ITP_CLK1
49.9_1%
C6
A20M#
B6
FERR#/PBE#
B2
IGNNE#
D1
LINT0
E5
LINT1
B5
SMI#
Y4
STPCLK#
B3
THERMDA
C4
THERMDC
PM_THRMTRIP#
A2
THERMTRIP#
C3
PROCHOT#
H_TESTHI5
3
AC23
TESTHI5
H_TESTHI4
2
AC24
TESTHI4
H_TESTHI3
3
AC20
TESTHI3
H_TESTHI2
2
AC21
TESTHI2
H_TESTHI1
4
AA2
TESTHI1
H_TESTHI0
1
AD24
TESTHI0
ITPCLKOUT0
ITPCLKOUT1
TP_CPU_NC0
A22
NC0
TP_CPU_NC1
A7
NC1
AD2
NC2
AD3
NC3
TP_CPU_NC4
AE21
NC4
VCC_VID_CPU_D
AF3
NC5
TP_CPU_NC6
AF24
NC6
TP_CPU_NC7
AF25
NC7
Processor-MobilSkt
B
C
8
8
8
4,5,9,10,18,20,40,41,47,48
+VCC_IMVP
R2T1
56
7
56
220
5
56
6
8
H_BR0#
8
8
8
+VCC_IMVP
8
RP2D1A
56
1
8
18,37
+VCC_IMVP
R3R1
NO_STUFF_51
H_CPURST# 5,8
H_RS#2
8
H_RS#1
8
H_RS#0
8
8
8
H_TRDY# 8
8
H_HIT#
8
H_HITM# 8
+VCC_IMVP
R2T3
300
AD6
H_BSEL0 6
BSEL0
AD5
H_BSEL1 6
FSBSEL1
A6
GHI#
PM_CPUPERF# 19,37
AD25
H_DPSLP# 7,18,37
DPSLP#
AB26
SLP#
H_CPUSLP# 18,37
H_COMP0
R3R5
61.9_1%
L24
COMP0
H_COMP1
R2R5
61.9_1%
P1
COMP1
TP_GTLREF3
AA21
GTLREF3
AA6
GTLREF2
TP_GTLREF1
F20
GTLREF1
TP_GTLREF0
F6
GTLREF0
AB4
H_BPM5_PREQ# 5
BPM5#
AA5
H_BPM4_PRDY# 5
BPM4#
Y6
BPM3#
H_BPM3_ITP# 5
AC4
BPM2#
H_BPM2_ITP# 5
AB5
BPM1#
H_BPM1_ITP# 5
AC6
H_BPM0_ITP# 5
BPM0#
H_ITPCLKOUT0
56
RP3C1A
AA20
1
8
H_ITPCLKOUT1
56
RP4C1D
AB22
4
5
AE25
ITP_DBRESET# 5,44,47
DBR#
D4
H_TCK
TCK
C1
H_TDI
TDI
D5
H_TDO
TDO
F7
H_TMS
TMS
E6
H_TRST# 5
TRST#
TP_CPU_SKTOCC#
R1F9
AF26
SKTOCC#
680
C
D
U2E1A
H_D#[15:0]
H_D#15
D25
D15#
H_D#14
J21
D14#
H_D#13
D23
D13#
H_D#12
C26
D12#
H_D#11
H21
D11#
H_D#10
G22
D10#
H_D#9
B25
D9#
H_D#8
C24
D8#
H_D#7
C23
D7#
H_D#6
B24
D6#
H_D#5
D22
D5#
H_D#4
C21
D4#
H_D#3
A25
D3#
H_D#2
A23
D2#
H_D#1
B22
D1#
H_D#0
B21
D0#
E21
H_DINV#0
DBI0#
E22
H_DSTBN#0
DSTBN0#
F21
H_DSTBP#0
DSTBP0#
H_D#[31:16]
H_D#31
H25
D31#
H_D#30
K23
D30#
H_D#29
J24
D29#
H_D#28
L22
D28#
H_D#27
M21
D27#
H_D#26
H24
D26#
H_D#25
G26
D25#
H_D#24
L21
D24#
H_D#23
D26
D23#
H_D#22
F26
D22#
H_D#21
E25
D21#
H_D#20
F24
D20#
H_D#19
F23
D19#
H_D#18
G23
D18#
H_D#17
E24
D17#
H_D#16
H22
D16#
G25
H_DINV#1
DBI1#
K22
H_DSTBN#1
DSTBN1#
J23
H_DSTBP#1
DSTBP1#
Processor-MobilSkt
4,5,9,10,18,20,40,41,47,48
+VCC_IMVP
Trace length: Less
than 1.5 inch
R2R2
51.1_1%
C2R6
C2R8
R2R4
86.6
220PF
1%
1UF
Place 1 GTLREF cap near
each pin under processor.
4,5,9,10,18,20,40,41,47,48
+VCC_IMVP
5
19
5
5
5
Title
Processor 1 of 2
Size
Project:
Custom
Date:
Friday, May 21, 2004
D
E
H_D#[47:32] 8
H_D#47
T23
D47#
H_D#46
T22
D46#
H_D#45
T25
D45#
H_D#44
T26
D44#
H_D#43
R24
D43#
H_D#42
R25
D42#
H_D#41
P24
D41#
H_D#40
R21
D40#
H_D#39
N25
D39#
H_D#38
N26
D38#
H_D#37
M26
D37#
H_D#36
N23
D36#
H_D#35
M24
D35#
H_D#34
P21
D34#
H_D#33
N22
D33#
H_D#32
M23
D32#
P26
H_DINV#2 8
DBI2#
R22
H_DSTBN#2 8
DSTBN2#
P23
H_DSTBP#2 8
DSTBP2#
H_D#[63:48] 8
H_D#63
AA24
D63#
H_D#62
AA22
D62#
H_D#61
AA25
D61#
H_D#60
Y21
D60#
H_D#59
Y24
D59#
H_D#58
Y23
D58#
H_D#57
W25
D57#
H_D#56
Y26
D56#
H_D#55
W26
D55#
H_D#54
V24
D54#
H_D#53
V22
D53#
H_D#52
U21
D52#
H_D#51
V25
D51#
H_D#50
U23
D50#
H_D#49
U24
D49#
H_D#48
U26
D48#
V21
H_DINV#3 8
DBI3#
W22
H_DSTBN#3 8
DSTBN3#
W23
H_DSTBP#3 8
DSTBP3#
H_GTLREF 47
4,5,9,10,18,20,40,41,47,48
+VCC_IMVP
R6H11
56
PM_THRMTRIP#
PM_THRMTRIP#
Document Number
Rev
Sheet
3
of
46
E
4
3
2
1
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