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2.3.2.2.
Integrated System Memory DRAM Controller
Supports up to two double-sided SO-DIMMs (four rows populated) with unbuffered PC2100 DDR-
SDRAM (with or without ECC)
Supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb technologies for x8 and x16 width devices
Up to 1 GB (with 256-Mb technology and two SO-DIMMs) of PC2100 DDR (with ECC) and up to
2 GB (high density using 512-Mb technology)
Supports 200-MHz and 266-MHz DDR devices
64-bit data interface (72-bit with ECC)
Supports up to 16 simultaneous open pages
Support for SO-DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power
management support via self refresh mode using CKE
2.3.2.3.
Internal Graphics Controller
Graphics Core Frequency
Display / Render frequency up to 133 MHz
3D Graphics Engine
3D Setup and Render Engine
Zone Rendering
High quality performance Texture Engine
Analog Display Support
350-MHz integrated 24-bit RAMDAC
Hardware color cursor support
Accompanying I2C and DDC channels provided through multiplexed interface
Dual independent pipe for dual independent display
Simultaneous display: same images and native display timings on each display device
Digital Video Out Port (DVOB & DVOC) support
DVOB & DVOC with 165-MHz dot clock support for each 12-bit interface
Compliant with DVI Specification 1.5
Dedicated LFP (local flat panel) support
Single or dual channel LVDS panel support up to UXGA panel resolution with frequency
range from 25 MHz to 112 MHz per channel
SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock
Supports data format of 18 bpp
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear Panel fitting
2.3.3.
Package/Power
732-pin Micro-FCBGA (37.5 mm x 37.5 mm)
VTTLF, VTTHF (1.05 V)
34
®
®
Intel
852GME, Intel
852GMV and Intel
®
852PM Chipset Platforms Design Guide
System Overview
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