Package Length Compensation; Dvob And Dvoc Routing Guidelines; Table 38. Dvob And Dvoc Routing Guideline Summary - Intel 852GME Design Manual

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7.3.2.2.

Package Length Compensation

As mentioned in Section 7.3.2.1, all length matching is done from the GMCH die-pad to the DVO
connector pin. The reason for this is to compensate for the package length variation across each signal
group in order to minimize timing variance. The GMCH does not equalize package lengths internally as
some previous GMCH components have, and therefore, the GMCH requires a length matching process.
See Table 39 for the DVOB package lengths information and see Table 40 for DVOC package lengths
information.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the minimum and maximum length bounds of a signal
group based on clock length, whereas package length compensation refers to the process of adjusting
out package length variance across a signal group. There is of course some overlap in that both affect
the target length of an individual signal. Intel recommends that the initial route be completed based on
the length matching formulas in conjunction with nominal package lengths and that package length
compensation be performed as secondary operation.
7.3.2.3.

DVOB and DVOC Routing Guidelines

Table 38 provides the DVOB and DVOC routing guideline summary.

Table 38. DVOB and DVOC Routing Guideline Summary

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DVO Signals
Minimum Spacing to Other DVO Signals
Minimum Spacing of DVOBCLK [1:0] or DVOCCLK
[1:0] to any other signals
Package Length Range – P1
Total Length –
Data to Clock Strobe Length Matching Requirements
CLK0 to CLK1 Length Matching Requirements
120
Parameter
® ®
Intel 852GME, Intel 852GMV and Intel
Integrated Graphics Display Port
Definition
DVOBD [11:0], DVCBD [11:0]
Point to point
Ground Referenced
55 ± 15%
Inner layers: 4 mils
2 to 1 (e.g. 8 mil space to 4 mil trace)
20 mils
12 mils (see exceptions for breakout region below)
12 mils
See Table 39 and Table 40 for package lengths.
Max 6"
+ 100 mils (See Table 37 for length matching requirements)
+ 10 mils (See Table 37 for length matching requirements.)
®
852PM Chipset Platforms Design Guide