Intel 852GME Design Manual page 15

R
Tables
Table 1. System Bus Routing Summary for the Processor..................................................... 41
Table 2. Processor System Bus Data Signal Routing Guidelines........................................... 45
Table 3. Processor System Bus Address Signal Routing Guidelines ..................................... 45
Table 4. Processor System Bus Control Signal Routing Guidelines....................................... 46
Table 5. Layout Recommendations for Topology 1A .............................................................. 47
Table 6. Layout Recommendations for Topology 1B .............................................................. 48
Table 7. Layout Recommendations for Topology 1C.............................................................. 49
Table 8. Layout Recommendations for Topology 2A .............................................................. 50
Table 9. Layout Recommendations for Topology 2B .............................................................. 51
Table 10. Layout Recommendations for Topology 2C............................................................ 52
Table 11. Layout Recommendations for Topology 3 .............................................................. 53
Table 12. Layout Recommendation for COMP[1:0] ................................................................ 55
Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector........ 57
Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths........... 58
Table 15. GMCH/MCH Chipset Memory Signal Groups ......................................................... 65
Table 16. Intel 852GME/852GMV/852PMChipset GMCH/MCH DDR 333 Length Matching
Formulas .................................................................................................................. 66
Table 17. Clock Signal Mapping.............................................................................................. 67
Table 18. Clock Signal Group Routing Guidelines.................................................................. 68
Table 19. Memory Clock Package Lengths............................................................................. 71
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing
Guidelines ................................................................................................................ 74
Table 21. SDQ/SDM to SDQS Mapping.................................................................................. 77
Table 22. Memory SDQ/SDM/SDQS Package Lengths ......................................................... 79
Table 23. Control Signal to SO-DIMM Mapping ...................................................................... 81
Table 24. Control Signal Routing Guidelines .......................................................................... 82
Table 25. Control Group Package Lengths ............................................................................. 86
Table 26. Command Topology 1 Routing Guidelines ............................................................. 88
Table 27. Command Topology 2 Routing Guidelines ............................................................. 92
Table 28. Command Topology 3 Routing Guidelines ............................................................. 97
Table 29. Command Group Package Lengths...................................................................... 100
Table 30. CPC Signal to SO-DIMM Mapping ........................................................................ 101
Table 31. CPC Signal Routing Guidelines ............................................................................ 102
Table 32. CPC Group Package Lengths ............................................................................... 104
Table 33. Recommended GMCH DAC Components............................................................ 112
Table 34. Signal Group and Signal Pair Names ................................................................... 115
Table 35. LVDS Signal Group Routing Guidelines ............................................................... 116
Table 36. LVDS Package Lengths ........................................................................................ 117
Table 37. DVO Interface Trace Length Mismatch Requirements ......................................... 119
Table 38. DVOB and DVOC Routing Guideline Summary.................................................... 120
Table 39. DVOB Interface Package Lengths ........................................................................ 121
Table 40. DVOC Interface Package Lengths ........................................................................ 122
Table 41. Allowable Interconnect Skew Calculation ............................................................. 124
Table 42. DVO Enabled Routing Guideline Summary .......................................................... 125
Table 43. GMBUS Pair Mapping and Options....................................................................... 126
Table 44. AGP 2.0 Signal Groups ......................................................................................... 129
Table 45. AGP 2.0 Data/Strobe Associations ....................................................................... 130
Table 46. Layout Routing Guidelines for AGP 1X Signals .................................................... 131
Table 47. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 133
® ®
Intel 852GME, Intel 852PM and Intel
®
852GMV Chipset Platforms Design Guide
15