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Chapter 4, Status Reporting
Setting up an SRQ Interrupt
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COM /Io_names/ INTEGER Hardware1_reg,Srq_enab_reg,Status_byte,Event_reg
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!
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!Turn off interrupts while processing the current interrupt.
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OFF INTR 7
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!
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!Conduct a SERIAL POLL to read the Status Byte and clear the SRQ:
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!
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Status_byte=SPOLL(Inst_address)
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!
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! Determine which Register Group(s) caused the interrupt. Since three
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! were enabled, all three must be checked:
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!
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IF BIT(Status_byte,5) THEN GOSUB Srvice_std_evnt
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IF BIT(Status_byte,3) THEN GOSUB Srvice_calib
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IF BIT(Status_byte,0) THEN GOSUB Srvice_hard1
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!
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! Re-enable the interrupt before leaving the service routine
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!
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ENABLE INTR 7;2
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SUBEXIT
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!
1440 Srvice_std_evnt:!
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! This routine would determine which bit(s) in the Standard Event
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! Status Register are TRUE, logic 1, and take appropriate action.
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! NOTE: Read the Event Register to clear it. If the Event Register is
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! not cleared it will NOT latch another event, thereby preventing
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! the E8285A from generating another SRQ.
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!
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OUTPUT Inst_address;"*ESR?"
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ENTER Inst_address;Event_reg
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RETURN
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!
1550 Srvice_calib:!
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! This routine would determine which bit(s) in the Calibration Status
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! Register Group Event Register are TRUE, logic 1, and take
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! appropriate action.
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! NOTE: Read the Event Register to clear it. If the Event Register is
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! not cleared it will NOT latch another event from the Condition
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! Register, thereby preventing the E8285A from generating another SRQ.
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!
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OUTPUT Inst_address;"STAT:CAL:EVEN?"
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ENTER Inst_address;Event_reg
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RETURN
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!
1670 Srvice_hard1:!
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! This routine would determine which bit(s) in the Hardware Status
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! Register #1 Group Event Register are TRUE, logic 1, and take
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! appropriate action.
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! NOTE: Read the Event Register to clear it. If the Event Register is
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! not cleared it will NOT latch another event from the Condition
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! Register, thereby preventing the E8285A from generating another SRQ.
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!
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OUTPUT Inst_address;"STAT:HARD1:EVEN?"
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ENTER Inst_address;Event_reg
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RETURN
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!
1790 SUBEND
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