Renesas H8/36912 Series User Manual page 19

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/36912 Group.................................................................3
Figure 1.2 Internal Block Diagram of H8/36902 Group.................................................................4
Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32).........................................................5
Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32).........................................................6
Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32) ...........................................................7
Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32) ...........................................................8
Section 2 CPU
Figure 2.1 Memory Map (1) .........................................................................................................12
Figure 2.1 Memory Map (2) .........................................................................................................13
Figure 2.2 CPU Registers .............................................................................................................14
Figure 2.3 Usage of General Registers .........................................................................................15
Figure 2.4 Relationship between Stack Pointer and Stack Area ...................................................16
Figure 2.5 General Register Data Formats (1) ..............................................................................18
Figure 2.5 General Register Data Formats (2) ..............................................................................19
Figure 2.6 Memory Data Formats.................................................................................................20
Figure 2.7 Instruction Formats......................................................................................................30
Figure 2.8 Branch Address Specification in Memory Indirect Mode ...........................................33
Figure 2.9 On-Chip Memory Access Cycle..................................................................................36
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................37
Figure 2.11 CPU Operation States................................................................................................38
Figure 2.12 State Transitions ........................................................................................................38
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address......................................................................................................................40
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................54
Figure 3.2 Stack Status after Exception Handling ........................................................................55
Figure 3.3 Interrupt Sequence.......................................................................................................57
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure ..............58
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................59
Figure 4.2 Address Break Interrupt Operation Example (1) .........................................................63
Figure 4.2 Address Break Interrupt Operation Example (2) .........................................................64
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators..................................................................65
Figure 5.2 State Transition of System Clock ................................................................................71
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled...................................72
Rev. 1.00, 11/03, page xix of xxviii
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