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15.3.4 I
15.3.5 I
15.3.6 Slave Address Register (SAR) .............................................................................236
15.3.7 I
15.3.8 I
15.3.9 I
15.4 Operation...........................................................................................................................238
15.4.2 Master Transmit Operation ..................................................................................239
15.4.3 Master Receive Operation....................................................................................241
15.4.4 Slave Transmit Operation ....................................................................................243
15.4.5 Slave Receive Operation ......................................................................................244
15.4.6 Clocked Synchronous Serial Format....................................................................246
15.4.7 Noise Canceler .....................................................................................................248
15.4.8 Example of Use....................................................................................................249
15.5 Interrupts ...........................................................................................................................253
15.6 Bit Synchronous Circuit.................................................................................................... 254
Section 16 A/D Converter................................................................................. 255
16.1 Features .............................................................................................................................255
16.2 Input/Output Pins ..............................................................................................................257
16.3 Register Description..........................................................................................................257
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................257
16.3.2 A/D Control/Status Register (ADCSR)................................................................258
16.3.3 A/D Control Register (ADCR).............................................................................259
16.4 Operation...........................................................................................................................261
16.4.1 Single Mode .........................................................................................................261
16.4.2 Scan Mode ...........................................................................................................261
16.4.3 Input Sampling and A/D Conversion Time..........................................................262
16.4.4 External Trigger Input Timing .............................................................................263
16.5 A/D Conversion Accuracy Definitions .............................................................................264
16.6 Usage Notes ......................................................................................................................266
16.6.1 Permissible Signal Source Impedance .................................................................266
16.6.2 Influences on Absolute Accuracy ........................................................................266
17.1 Features .............................................................................................................................268
17.2 Register Descriptions ........................................................................................................269
17.2.1 Low-Voltage-Detection Control Register (LVDCR) ...........................................269
17.2.2 Low-Voltage-Detection Status Register (LVDSR) ..............................................271
17.3 Operations .........................................................................................................................272
17.3.1 Power-On Reset Circuit .......................................................................................272
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2
C Bus Interrupt Enable Register (ICIER)..........................................................232
2
C Bus Status Register (ICSR)............................................................................234
2
C Bus Transmit Data Register (ICDRT) ...........................................................237
2
C Bus Receive Data Register (ICDRR).............................................................237
2
C Bus Shift Register (ICDRS)...........................................................................237
2
C Bus Format ....................................................................................................238
Circuits............................................................................................ 267
Rev. 1.00, 11/03, page xv of xxviii
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