Renesas H8/36912 Series User Manual page 20

Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From Internal RC Clock to External Clock)............................................................... 73
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2)
(From External Clock to Internal RC Clock)............................................................... 74
Figure 5.6 Timing Chart of Switching Internal RC Clock to External Clock............................... 75
Figure 5.7 Timing Chart to Switch External Clock to Internal RC Clock .................................... 76
Figure 5.8 External Oscillation Backup Timing ........................................................................... 77
Figure 5.9 Example of Trimming Flow for Internal RC Oscillator Frequency............................. 78
Figure 5.10 Timing Chart of Trimming of Internal RC Oscillator Frequency.............................. 79
Figure 5.11 Example of Connection to Crystal Resonator ........................................................... 80
Figure 5.12 Equivalent Circuit of Crystal Resonator.................................................................... 80
Figure 5.13 Example of Connection to Ceramic Resonator.......................................................... 81
Figure 5.14 Example of External Clock Input .............................................................................. 81
Figure 5.15 Example of Incorrect Board Design .......................................................................... 82
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ...........................................................................................89
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 95
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode .......................... 102
Figure 7.3 Program/Program-Verify Flowchart.......................................................................... 104
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 107
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 111
Figure 9.2 Port 2 Pin Configuration............................................................................................ 115
Figure 9.3 Port 5 Pin Configuration............................................................................................ 117
Figure 9.4 Port 7 Pin Configuration............................................................................................ 121
Figure 9.5 Port 8 Pin Configuration............................................................................................ 123
Figure 9.6 Port B Pin Configuration ........................................................................................... 127
Figure 9.7 Port C Pin Configuration ........................................................................................... 130
Section 10 Timer B1
Figure 10.1 Block Diagram of Timer B1.................................................................................... 133
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V...................................................................................... 138
Figure 11.2 Increment Timing with Internal Clock .................................................................... 144
Figure 11.3 Increment Timing with External Clock ................................................................... 145
Figure 11.4 OVF Set Timing ...................................................................................................... 145
Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 145
Figure 11.6 TMOV Output Timing ............................................................................................ 146
Figure 11.7 Clear Timing by Compare Match............................................................................ 146
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 146
Figure 11.9 Pulse Output Example ............................................................................................. 147
Rev. 1.00, 11/03, page xx of xxviii
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