Figure 15.1 Block Diagram Of I - Renesas H8/36912 Series User Manual

SCL
Noise canceler
SDA
Noise canceler
[Legend]
2
ICCR1: I
2
ICCR2: I
2
ICMR: I
2
ICSR: I
2
ICIER: I
2
ICDRT: I
2
ICDRR: I
2
ICDRS: I
SAR: Slave address register
Rev. 1.00, 11/03, page 226 of 376
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Output
control
Output
control
Bus state
decision circuit
Arbitration
decision circuit
C bus control register 1
C bus control register 2
C bus mode register
C bus status register
C bus interrupt enable register
C bus transmit data register
C bus receive data register
C bus shift register

Figure 15.1 Block Diagram of I

Transmit/
receive
control circuit
ICDRT
ICDRS
ICDRR
ICIER
2
C Bus Interface 2
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Address
comparator
ICSR
Interrupt
Interrupt request
generator