Timer Status Register W (Tsrw) - Renesas H8/36912 Series User Manual

12.3.4

Timer Status Register W (TSRW)

TSRW shows the status of interrupt requests.
Bit Bit Name
7 OVF

6 to 4
3 IMFD
2 IMFC
Rev. 1.00, 11/03, page 158 of 376
Downloaded from Elcodis.com electronic components distributor
Initial
Value R/W Description
0 R/W Timer Overflow Flag
[Setting condition]
•
[Clearing condition]
•

All 1 Reserved
These bits are always read as 1.
0 R/W Input Capture/Compare Match Flag D
[Setting conditions]
•
•
[Clearing condition]
•
0 R/W Input Capture/Compare Match Flag C
[Setting conditions]
•
•
[Clearing condition]
•
When TCNT overflows from H'FFFF to H'0000
Read OVF when OVF = 1, then write 0 in OVF
TCNT = GRD when GRD functions as an output
compare register
The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
Read IMFD when IMFD = 1, then write 0 in IMFD
TCNT = GRC when GRC functions as an output
compare register
The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
Read IMFC when IMFC = 1, then write 0 in IMFC