Core Deep Power Down Technology (Code Name C6) State; Package Low-Power State Descriptions; Normal State; Stop-Grant State - Intel P8700 - Core 2 Duo Processor Datasheet

Low Power Features
2.1.1.7

Core Deep Power Down Technology (Code Name C6) State

Deep Power Down Technology state is a new, power-saving state which is being
implemented on the processor. In Deep Power Down Technology the processor saves its
entire architectural state onto an on-die SRAM hence allowing it to lower its main core
voltage to any value, even as low as 0-V.
When the core enters Deep Power Down Technology state, it saves the processor state
that is relevant to the processor context in an on-die SRAM that resides on a separate
power plane V
any arbitrary voltage including 0-V. The on-die storage for saving the processor state is
implemented as a per-core SRAM.
2.1.2

Package Low-power State Descriptions

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT
state.
2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each core of the dual-core processor enters the
Stop-Grant state within 20 bus clocks after the response phase of the processor-issued
Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,
C3, or C4 state remain in their current low-power state. When the STPCLK# pin is
deasserted, each core returns to its previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to V
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,
DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC
Specification T45. When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification
T75.
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or Monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor
should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop
on the FSB (see
occurs with the assertion of the SLP# signal.
Datasheet
(I/O power supply). This allows the main core Vcc to be lowered to
CCP
Section 2.1.2.3). A transition to the Sleep state (see
) for minimum power drawn by the
CCP
Section 2.1.2.4)
15