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(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
3.1.2 Internal data memory space
The µ PD178054 Subseries products incorporate the following RAMs.
(1) Internal high-speed RAM
The µ PD178053, 178054, and 178F054 have a RAM structure of 1024 × 8 bits.
In this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated
in the 32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory area.
3.1.3 Special Function Register (SFR) area
An on-chip peripheral hardware special function register (SFR) is allocated in the area FF00H to FFFFH. Refer
to Table 3-4 Special Function Registers.
Caution Do not access addresses where the SFR is not assigned.
CHAPTER 3 CPU ARCHITECTURE
User's Manual U15104EJ2V0UD
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