System Clock And Cpu Clock Switching Procedure - NEC mPD780344 Series User Manual

5.6.2 System clock and CPU clock switching procedure

This section describes the procedure for switching between the system clock and CPU clock.
V
DD
RESET
Interrupt request signal
System clock
CPU clock
<1> The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation
stabilization time (2 17
After that, the CPU starts executing instructions at the minimum speed of the main system clock (3.2 µ s @10
MHz operation).
<2> After the lapse of a sufficient time for the V
PCC is rewritten and maximum-speed operation is carried out.
<3> Upon detection of a decrease of the V
switched to the subsystem clock (which must be in an oscillation stable state).
<4> Upon detection of V
DD
main system clock is started. After the lapse of time required for stabilization of oscillation, PCC is rewritten
and the maximum-speed operation is resumed.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
126
CHAPTER 5 CLOCK GENERATOR
Figure 5-9. System Clock and CPU Clock Switching
f
X
Lowest-
speed
operation
Wait (13.1 ms: @10 MHz operation)
Internal reset operation
/f ) is secured automatically.
X
voltage to increase to enable operation at maximum speeds, the
DD
voltage due to an interrupt request signal, the main system clock is
DD
voltage reset due to an interrupt, bit 7 (MCC) of PCC is set to 0 and oscillation of the
User's Manual U15798EJ2V0UD
f f
X XT
Highest- Subsystem
speed clock
operation operation
f
X
High-speed
operation