Power Sequencing Timing Definitions - Intel 810A3 Design Manual

System Design Considerations
Table 7-3. Power Sequencing Timing Definitions
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
NOTE: * This value is board dependent.
7-12
Parameter
VccSUS Good to RSMRST# inactive
VccSUS Good to SLP_S3#, SLP_S5#, and PCIRST# active
RSMRST# inactive to SLP_S3# inactive
RSMRST# inactive to SLP_S5# inactive
RSMRST# inactive to SUS_STAT# inactive
SLP_S3#, SLP_S5#, SUS_STAT# inactive to Vcc3.3core good
Vcc3.3core good to CPUSLP# inactive
Vcc3.3core good to PWROK active
Vcc3.3core good to clocks valid
Clocks valid to PCIRST# inactive
PWROK active to PCIRST# inactive
PCIRST# inactive to Cycle 1 from GMCH
Cycle 1 from ICH to Cycle 2 from GMCH
PCIRST# inactive to STPCLK de-assertion
PCIRST# to frequency straps valid
Cycle 2 from ICH to frequency straps invalid
Cycle 2 from ICH to CPURST# inactive
Stop Grant Cycle to CPUSLP# active
CPUSLP# active to SUS_STAT# active
SUS_STAT# active to PCIRST# active
PCIRST# active to SLP_S3# active
PWROK inactive to Vcc3.3core not good
Wake event to SLP_S3# inactive
PCIRST# inactive to STPCLK# inactive
SLP_S3# active to SLP_S5# active
SLP_S5# inactive to SLP_S3# inactive
Min. Max.
1 25 ms
50 ns
1 4 RTC clocks
1 4 RTC clocks
1 4 RTC clocks
* *
50 ns
* *
* *
500 us
.9 1.1 ms
1 ms
60 ns
1 4 PCI clocks
-4 4 PCI clocks
180 ns
110 ns
8 PCI clocks
1 RTC clock
2 3 RTC clocks
1 2 RTC clocks
20 ns
2 3 RTC clocks
1 4 PCI clocks
1 2 RTC clocks
2 3 RTC clocks
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Intel 810A3 Chipset Design Guide
Units