I2C Bus - Xilinx KCU116 User Manual

Table 3-17 lists the connections between the U5 ADV7511 codec and the HDMI connector
P2.
Table 3‐17: HDMI ADV511 Codec U52 to P6 Connections
ADV7511 (U54)
Name
TX0_P
TX0_N
TX1_P
TX1_N
TX2_P
TX2_N
TXC_P
TXC_N
DDCSDA
DDCSCL
HEAC_P
HEAC_N
CEC
For more information about the Analog Devices ADV7511KSTZ-P, see the Analog Devices
website [Ref 30]. For additional information about HDMI IP options, see the DisplayPort
LogiCORE Product Guide (PG064)

I2C Bus

[Figure 2-1, callouts 20, 21]
The KCU116 evaluation board implements a 2-to-1 I
from each of the FPGA U1 XCKU5P (IIC_MAIN_SCL/SDA_LS) and system controller
Zynq-7000 SoC U111 (SYSCTLR_I2C_SCL/SDA) are wired to the same I
level-shifters (FPGA U1 is wired through level-shifter U162 and system controller U161 is
wired through level-shifter U163). The output sides of U162 and U163 are wired in parallel
2
to a common I
pair of 1-to-8 channel I2C TI PCA9548 bus switches (U34 and U135) and a TI TCA6416A I2C
GPIO expander (U147). The bus switches can operate at speeds up to 400 kHz.
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Pin
36
35
40
39
43
42
33
32
54
53
52
51
48
[Ref
C bus (IIC_SDA and _SCL_MAIN). This common I
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Chapter 3: Board Component Descriptions
Schematic Net Name
HDMI_D0_P
HDMI_D0_N
HDMI_D1_P
HDMI_D1_N
HDMI_D2_P
HDMI_D2_N
HDMI_CLK_P
HDMI_CLK_N
HDMI_DDCSDA
HDMI_DDCSCL
HDMI_HEAC_P
HDMI_HEAC_N
HDMI_CEC
19].
2
C bus arrangement. A single I
HDMI Connector P6 Pin
7
9
4
6
1
3
10
12
16
15
14
19
13
2
C bus
2
C bus via
2
C bus is then routed to a
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54