I2C Bus Switch - Xilinx KC705 User Manual

Table 1-23
Table 1-23: FPGA to LCD Header Connections
For more information about the Displaytech S162D LCD, see

I2C Bus Switch

[Figure
The KC705 board implements a single I
IIC_SDA_SCL), which is routed through a TI PCA9548 1-to-8 channel I
U49 pin 24 net IIC_MUX_RESET_B is connected to U1 bank 15 pin P23. This is an
active-Low signal and must be driven High (FPGA U1 pin P23) to enable I
transactions between the FPGA U1 and the other components on the I
switch can operate at speeds up to 400 kHz. The U49 bus switch at I
0b01110100 must be addressed and configured to select the desired target back-side
device.
The KC705 board I
X-Ref Target - Figure 1-23
User applications that communicate with devices on one of the downstream I
must first set up a path to the desired bus through the U49 bus switch at I
0b01110100.
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
lists the connections between the FPGA and the LCD header.
FPGA Pin (U1) Schematic Net Name
AA13 LCD_DB4_LS
AA10 LCD_DB5_LS
AA11 LCD_DB6_LS
Y10 LCD_DB7_LS
AB13 LCD_RW_LS
Y11 LCD_RS_LS
AB10 LCD_E_LS
1-2, callout 20]
2
C bus topology is shown in
U1
FPGA
Bank 15
(2.5V)
IIC_SDA/SCL_MAIN
www.xilinx.com
I/O Standard
LVCMOS15
LVCMOS15
LVCMOS15
LVCMOS15
LVCMOS15
LVCMOS15
LVCMOS15
2
C port on the FPGA (IIC_SDA_MAIN,
Figure
U49
PCA9548
1 2 C 1-to-8
Bus Switch
2
Figure 1-23: I C Bus Topology
Feature Descriptions
LCD Header Pin (J31)
4
3
2
1
10
11
9
[Ref 18].
2
C switch (U49).
2
C bus
2
C bus. The I
2
C address 0x74/
1-23.
CH0 - USER_CLOCK_SDA/SCL
CH1 - FMC_HPC_IIC_SDA/SCL
CH2 - FMC_LPC_IIC_SDA/SCL
CH3 - EEPROM_IIC_SDA/SCL
CH4 - SFP_IIC_SDA/SCL
CH5 - IIC_SDA/SCL_HDMI
CH6 - IIC_SDA/SCL_DDR3
CH7 - SI5326_SDA/SCL
UG810_C1_23_031214
2
C buses
2
C address 0x74/
Send Feedback
2
C
47