I2C Bus Management - Xilinx Kintex-7 FPGA KC724 User Manual

I2C Bus Management

Callout 32,
The I2C bus is controlled through U39, an 8-channel I2C-bus multiplexer (NXP
Semiconductor PCA9547). The FPGA communicates with the multiplexer through I2C
data and clock signals mapped to FPGA pins E21 and F21, respectively. The I2C idcode for
the PCA9547 device is 0x70. The bus hosts four components:
•
•
•
•
An I2C component can be accessed by selecting the appropriate channel through the
control register of the MUX as shown in
Table 1-20: I2C Channel Assignments
U39 Channel
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
Figure 1-2.
SuperClock-2 module
7 series GTX transceiver power supply module
FMC1
FMC2
I2C Component
0 SuperClock-2 module
1 7 series GTX transceiver power supply module
2 FMC1
3 FMC2
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Table 1-20.
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