I2C Bus Switch - Xilinx AC701 User Manual

Table 1-21
the J23 pins listed in
Table 1-21: FPGA to LCD Header Connections
For the Displaytech S162DBABC LCD data sheet, see

I2C Bus Switch

[Figure
The AC701 board implements a single I2C port on FPGA Bank 14 (IIC_SDA_MAIN, FPGA pin
K25 and IIC_SCL_MAIN, FPGA pin N18), which is routed through a Texas Instruments PCA9548
1-to-8 channel I2C switch (U52). The I2C switch can operate at speeds up to 400 kHz. The U52 bus
switch at I2C address 0x74/0b01110100 must be addressed and configured to select the desired
target downstream device.
The AC701 board I2C bus topology is shown in
X-Ref Target - Figure 1-29
User applications that communicate with devices on one of the downstream I2C buses must first set
up a path to the desired bus through the U52 bus switch at I2C address 0x74/0b01110100.
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
lists the connections between the FPGA and the LCD header. If the LCD is not installed,
Table 1-21
FPGA Pin (U1) Schematic Net Name
L25 LCD_DB4_LS
M24 LCD_DB5_LS
M25 LCD_DB6_LS
L22 LCD_DB7_LS
L24 LCD_RW_LS
L23 LCD_RS_LS
L20 LCD_E_LS
1-2, callout 19]
U1
FPGA
Bank 14
(3.3V)
IIC_SDA/SCL_MAIN
Figure 1-29: I2C Bus Topology
www.xilinx.com
can be used for GPIO.
I/O Standard
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
[Ref 23].
Figure 1-29.
U52
PCA9548
1 2 C 1-to-8
Bus Switch
CH0 - USER_CLK_SDL/SCL
CH1 - FMC_HPC_IIC_SDA/SCL
CH2 - (NOT USED)
CH3 - EEPROM_IIC_SDA/SCL
CH4 - SFP_IIC_SDA/SCL
CH5 - IIC_SDA/SCL_HDMI
CH6 - IIC_SDA/SCL_DDR3
CH7 - SI5324_SDA/SCL
0x74
Feature Descriptions
LCD Header Pin (J23)
4
3
2
1
10
11
9
UG952_C1_27_100312
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